MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1015

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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DDRH[7:0]
Reset
Reset
This register always reads back the buffered state of the associated pins. This can also be used to
detect overload or short circuit conditions on output pins.
24.0.5.44 Port H Data Direction Register (DDRH)
Read: Anytime.
Write: Anytime.
This register configures each port H pin as either input or output.
If the associated routed SPI module is enabled this register has no effect on the pins.
If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRH bits revert to controlling the I/O direction of a pin when the associated peripheral
modules are disabled.
Field
24.0.5.45 Port H Reduced Drive Register (RDRH)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each Port H output pin as either full or reduced. If the
port is used as input this bit is ignored.
7–0
W
W
R
R
DDRH7
RDRH7
Data Direction Port H
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
7
0
7
0
on PTH or PTIH registers, when changing the DDRH register.
DDRH6
RDRH6
0
0
6
6
Figure 24-47. Port H Reduced Drive Register (RDRH)
Figure 24-46. Port H Data Direction Register (DDRH)
Table 24-41. DDRH Field Descriptions
DDRH5
RDRH5
5
0
5
0
DDRH4
RDRH4
0
0
4
4
Description
DDRH3
RDRH3
3
0
3
0
DDRH2
RDRH2
0
0
2
2
DDRH1
RDRH1
1
0
1
0
DDRH0
RDRH0
0
0
0
0

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