MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1030

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Port K pin PE[7] is configured for reduced input threshold in certain modes (refer to S12X_EBI section).
24.0.7.5
This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose
I/O, or with the channels of the enhanced capture timer.
24.0.7.6
This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:0] can be used either for general-
purpose I/O, or with the SCI and SPI subsystems.
The SPI0 pins can be re-routed. Refer to
24.0.7.7
This port is associated with the CAN4 and 0 and SPI0. Port M pins PM[7:0] can be used for either general
purpose I/O, or with the CAN, SCI and SPI subsystems.
The CAN0, CAN4 and SPI0 pins can be re-routed. Refer to
(MODRR)”.
24.0.7.8
This port is associated with the PWM, SPI1. Port P pins PP[7:0] can be used for either general purpose I/
O, or with the PWM and SPI subsystems.
The pins are shared between the PWM channels and the SPI1. If the PWM is enabled the pins become
PWM output channels with the exception of pin 7 which can be PWM input or output. If SPI1is enabled
and PWM is disabled, the respective pin configuration is determined by status bits in the SPI.
The SPI1 pins can be re-routed. Refer to
Port P offers 8 I/O pins with edge triggered interrupt capability in wired-OR fashion
Interrupts”).
1032
Port T
Port S
Port M
Port P
Port K is not available in 80-pin packages.
PS[7:4] are not available in 80-pin packages.
PM[7:6] are not available in 80-pin packages.
PP[6] is not available in 80-pin packages.
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 24.0.5.33, “Module Routing Register
Section 24.0.5.33, “Module Routing Register
NOTE
NOTE
NOTE
NOTE
Section 24.0.5.33, “Module Routing Register
(Section 24.0.8, “Pin
Freescale Semiconductor
(MODRR)”.
(MODRR)”.