MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1031

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.0.7.9
This port is associated with the SPI1, . Port H pins PH[7:0] can be used for either general purpose
I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1. Refer to
Section 24.0.5.33, “Module Routing Register
Port H offers 8 I/O pins with edge triggered interrupt capability
24.0.7.10 Port J
This port is associated with CAN4, CAN0, IIC0. Port J pins PJ[7:4] and PJ[2:0] can be used for
either general purpose I/O, or with the CAN, IIC, or SCI subsystems. If IIC takes precedence the
associated pins become IIC open-drain output pins. The CAN4 pins can be re-routed. Refer to
Section 24.0.5.33, “Module Routing Register
Port J pins can be used with the routed CAN0 modules. Refer to
Routing Register
Port J offers 7 I/O pins with edge triggered interrupt capability
24.0.7.11 Port AD1
This port is associated with the ATD1. Port AD1 pins PAD15–PAD0 can be used for either general
purpose I/O, or with the ATD1 subsystem.
24.0.8
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to
rising or falling edges can be individually configured on per-pin basis. All bits/pins in a port share
the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port
interrupt enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when
it is in STOP or WAIT mode.
A digital filter on each pin prevents pulses
generating an interrupt. The minimum time varies over process conditions, temperature and
voltage
(Figure 24-69
Pin Interrupts
Port H
Port H is not available in 80-pin packages.
PJ[5,4,2,1,0] are not available in 80-pin packages.
PAD[15:8] are not available in 80-pin packages.
(MODRR)”.
and
Table
24-62).
(Figure
NOTE
NOTE
NOTE
(MODRR)”.
(MODRR)”.
24-70) shorter than a specified time from
(Section 24.0.8, “Pin
(Section 24.0.8, “Pin
Section 24.0.5.33, “Module
Interrupts”).
Interrupts”).