MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1115

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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CBEIE, CCIE and KEYACC bits are readable and writable while all remaining bits read 0 and are not
writable in normal mode. KEYACC is only writable if KEYEN (see
Register (FSEC)”
mass erase and erase verify operations. When writing to the FCNFG register in special mode, all
unimplemented/ reserved bits must be written to 0.
Freescale Semiconductor
BKSEL[1:0]
KEYACC
Reset
Reset
CBEIE
Field
CCIE
1–0
7
6
5
W
W
R
R
CBEIE
CBEIE
Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command
buffer in the Flash module.
0 Command buffer empty interrupt disabled.
1 An interrupt will be requested whenever the CBEIF flag (see
Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been
completed in the Flash module.
0 Command complete interrupt disabled.
1 An interrupt will be requested whenever the CCIF flag (see
Enable Security Key Writing
0 Flash writes are interpreted as the start of a command write sequence.
1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid
Block Select — The BKSEL[1:0] bits indicates which register bank is active according to
0
0
7
7
(FSTAT)”)
is set.
data.
is set to the enabled state. BKSEL is readable and writable in special mode to simplify
Figure 27-8. Flash Configuration Register (FCNFG — Normal Mode)
Figure 27-9. Flash Configuration Register (FCNFG — Special Mode)
= Unimplemented or Reserved
= Unimplemented or Reserved
is set.
CCIE
CCIE
0
0
6
6
Table 27-10. Flash Register Bank Selects
BKSEL[1:0]
Table 27-9. FCNFG Field Descriptions
KEYACC
KEYACC
MC9S12XDP512 Data Sheet, Rev. 2.21
00
01
0
0
5
5
Undefined
Undefined
0
0
4
4
Description
Selected Block
Flash Block 0
Flash Block 1
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)
0
0
0
0
3
3
Section 27.3.2.6, “Flash Status Register
Section 27.3.2.6, “Flash Status Register
Section 27.3.2.2, “Flash Security
0
0
0
0
2
2
0
0
0
1
1
Table
BKSEL
27-10.
(FSTAT)”)
0
0
0
0
0
1117

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