MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 122

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 3 Pierce Oscillator (S12XOSCLCPV1)
3.2.3
The XCLKS is an input signal which controls whether a crystal in combination with the internal loop
controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock
circuitry is used. Refer to the Device Overview chapter for polarity and sampling conditions of the XCLKS
pin.
3.3
The CRG contains the registers and associated bits for controlling and monitoring the oscillator module.
3.4
The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal
level which is determined by the amount of hysteresis being used and the maximum oscillation range.
The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is
intended to be connected to either a crystal or an external clock source. The selection of loop controlled
Pierce oscillator or full swing Pierce oscillator/external clock depends on the XCLKS signal which is
sampled during reset. The XTAL pin is an output signal that provides crystal circuit feedback.
A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is
powered by the V
3.4.1
A closed loop control system will be utilized whereby the amplifier is modulated to keep the output
waveform sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be kept
above twice the maximum hysteresis level of the input buffer. Electrical specification details are provided
in the Electrical Characteristics appendix.
3.4.2
The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU
clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure
which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock
monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function
is enabled/disabled by the CME control bit, described in the CRG block description chapter.
122
.
Table 3-1
Memory Map and Register Definition
Functional Description
XCLKS — Input Signal
Gain Control
Clock Monitor
lists the state coding of the sampled XCLKS signal.
DDPLL
XCLKS
and V
1
0
Table 3-1. Clock Selection Based on XCLKS
SSPLL
Loop controlled Pierce oscillator selected
Full swing Pierce oscillator/external clock selected
MC9S12XDP512 Data Sheet, Rev. 2.21
power supply pins.
Description
Freescale Semiconductor

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