MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1230

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 30 Security (S12X9SECV2)
30.1.2
30.1.3
Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the
security bits located in the options/security byte in the Flash memory array. These non-volatile bits will
keep the device secured through reset and power-down.
The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory
array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used
for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte
is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this
byte are copied into the Flash security register (FSEC) during a reset sequence.
1232
1
2
3
Internal accesses visible
0xFF0F
EEPROM Array Access
Availability of Flash arrays in the memory map depends on ROMCTL/EROMCTL pins and/or the state of
the ROMON/EROMON bits in the MMCCTL1 register. Please refer to the S12X_MMC block guide for
detailed information.
Restricted NVM command set only. Please refer to the FTX/EETX block guides for detailed information.
BDM hardware commands restricted to peripheral registers only.
External Bus Interface
Internal status visible
Flash Array Access
DBG Module Trace
Modes of Operation
Securing the Microcontroller
XGATE Debugging
NVM Commands
on external bus
multiplexed on
external bus
BDM
KEYEN1
Table 30-1. Features Availability in Unsecure and Secure Modes
7
KEYEN0
6
Figure 30-1. Flash Options/Security Byte
NS
✔
—
—
—
✔
✔
✔
✔
✔
2
MC9S12XDP512 Data Sheet, Rev. 2.21
SS
—
—
—
✔
✔
✔
✔
✔
✔
NV5
Unsecure Mode
5
NX
✔
✔
—
—
✔
✔
✔
✔
✔
1
2
ES
✔
✔
—
✔
✔
✔
✔
✔
✔
NV4
1
2
4
EX
✔
✔
—
✔
✔
✔
✔
✔
✔
1
2
NV3
ST
✔
—
✔
✔
✔
✔
✔
✔
✔
3
1
NS
✔
—
—
—
—
—
—
✔
✔
2
NV2
SS
2
✔
✔
—
—
—
—
—
✔
✔
2
3
Secure Mode
NX
✔
—
—
—
—
—
—
—
✔
2
SEC1
1
ES
✔
—
—
—
—
—
—
✔
✔
2
Freescale Semiconductor
EX
✔
—
—
—
—
—
—
✔
✔
SEC0
2
0
ST
✔
—
—
—
—
—
—
✔
✔
2