MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1331

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x01C0–0x01FF Freescale Scalable CAN — MSCAN (CAN2) Map (continued)
Freescale Semiconductor
Address
0x01E0–
0x01F0–
0x01DC
0x01DD
0x01D1
0x01D2
0x01D3
0x01D4
0x01D5
0x01D6
0x01D7
0x01D8
0x01D9
0x01DA
0x01DB
0x01DE
0x01DF
0x01EF
0x01FF
CAN2IDMR0
CAN2IDMR1
CAN2IDMR2
CAN2IDMR3
CAN2IDMR4
CAN2IDMR5
CAN2IDMR6
CAN2IDMR7
CAN2IDAR1
CAN2IDAR2
CAN2IDAR3
CAN2IDAR4
CAN2IDAR5
CAN2IDAR6
CAN2IDAR7
CAN2RXFG
CAN2TXFG
Name
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit 7
AM7
AM7
AM7
AM7
AM7
AM7
AM7
AM7
AC7
AC7
AC7
AC7
AC7
AC7
AC7
(See
(See
MC9S12XDP512 Data Sheet, Rev. 2.21
Bit 6
AM6
AM6
AM6
AM6
AM6
AM6
AM6
AM6
AC6
AC6
AC6
AC6
AC6
AC6
AC6
Detailed MSCAN Foreground Receive and Transmit Buffer
Detailed MSCAN Foreground Receive and Transmit Buffer
Bit 5
AM5
AM5
AM5
AM5
AM5
AM5
AM5
AM5
AC5
AC5
AC5
AC5
AC5
AC5
AC5
FOREGROUND TRANSMIT BUFFER
FOREGROUND RECEIVE BUFFER
Bit 4
AM4
AM4
AM4
AM4
AM4
AM4
AM4
AM4
AC4
AC4
AC4
AC4
AC4
AC4
AC4
Bit 3
AM3
AM3
AM3
AM3
AM3
AM3
AM3
AM3
AC3
AC3
AC3
AC3
AC3
AC3
AC3
Appendix G Detailed Register Map
Bit 2
AM2
AM2
AM2
AM2
AM2
AM2
AM2
AM2
AC2
AC2
AC2
AC2
AC2
AC2
AC2
Bit 1
AM1
AM1
AM1
AM1
AM1
AM1
AM1
AM1
AC1
AC1
AC1
AC1
AC1
AC1
AC1
Layout)
Layout)
Bit 0
AM0
AM0
AM0
AM0
AM0
AM0
AM0
AM0
AC0
AC0
AC0
AC0
AC0
AC0
AC0
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