MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 168

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3.2.3
This register controls power down, interrupt and external trigger. Writes to this register will abort current
conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
168
ETRIGLE
Reset
ETRIGP
ETRIGE
ADPU
AFFC
AWAI
Field
W
7
6
5
4
3
2
R
ADPU
ATD Control Register 2 (ATDCTL2)
0
7
ATD Power Up — This bit provides on/off control over the ATD block allowing reduced MCU power
consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time
period after ADPU bit is enabled.
0 Power down ATD
1 Normal ATD functionality
ATD Fast Flag Clear All
0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to
1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will
ATD Power Down in Wait Mode — When entering wait mode this bit provides on/off control over the ATD block
allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires
a recovery time period after exit from Wait mode.
0 ATD continues to run in Wait mode
1 Halt conversion and power down ATD during wait mode
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 5-6
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See
details.
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of
the ETRIG3–0 inputs as described in
input buffer of this channel is enabled. The external trigger allows to synchronize sample and ATD conversions
processes with external events.
0 Disable external trigger
1 Enable external trigger
Note: If using one of the AD channel as external trigger (ETRIGSEL = 0) the conversion results for this channel
clear the associate CCF flag).
cause the associate CCF flag to clear automatically.
After exiting wait mode with an interrupt conversion will resume. But due to the recovery time the result of
this conversion should be ignored.
have no meaning while external trigger mode is enabled.
= Unimplemented or Reserved
for details.
AFFC
0
6
Figure 5-5. ATD Control Register 2 (ATDCTL2)
Table 5-5. ATDCTL2 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
AWAI
0
5
Table
ETRIGLE
5-4. If external trigger source is one of the AD channels, the digital
0
4
Description
ETRIGP
0
3
ETRIGE
0
2
Freescale Semiconductor
ASCIE
0
1
Table 5-6
ASCIF
for
0
0

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