MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 205

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 6-22
Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is
running on the RISC core. They both have a critical section of code that accesses the same system resource.
To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence
must be embedded in a semaphore lock/release sequence as shown.
6.4.5
The XGATE module will immediately terminate program execution after detecting an error condition
caused by erratic application code. There are three error conditions:
All opcodes which are not listed in section
and opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the
S12X_MMC Section for a detailed information.
Freescale Semiconductor
•
•
•
Execution of an illegal opcode
Illegal vector or opcode fetches
Illegal load or store accesses
Software Error Detection
gives an example of the typical usage of the XGATE hardware semaphores.
Figure 6-22. Algorithm for Locking and Releasing Semaphores
XGSEM
S12X_CPU
%1
XGSEM
sequence
critical
.........
.........
code
XGSEMx
MC9S12XDP512 Data Sheet, Rev. 2.21
%1?
%0
Section 6.8, “Instruction Set”
XGATE
sequence
critical
CSEM
SSEM
.........
BCC?
.........
code
are illegal opcodes. Illegal vector
Chapter 6 XGATE (S12XGATEV2)
205