MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 325

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.9
Read or write: Anytime
All bits reset to zero.
Freescale Semiconductor
EDG[7:0]B
EDG[7:0]A
7, 5, 3, 1
6, 4, 2, 0
Reset
Reset
Field
W
W
R
R
EDG7B
EDG3B
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits for each input capture channel. The four pairs of control bits in TCTL4 also configure the input capture
edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the
active edge for the 16-bit pulse accumulator PACB. See
Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
0
0
7
7
EDG7A
EDG3A
0
0
6
6
EDGxB
Table 7-12. Edge Detector Circuit Configuration
0
0
1
1
Figure 7-13. Timer Control Register 3 (TCTL3)
Figure 7-14. Timer Control Register 4 (TCTL4)
Table 7-11. TCTL3/TCTL4 Field Descriptions
EDG6B
EDG2B
MC9S12XDP512 Data Sheet, Rev. 2.21
EDGxA
0
0
5
5
0
1
0
1
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
EDG6A
EDG2A
0
0
4
4
Description
Configuration
Table
EDG5B
EDG1B
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
0
0
3
3
7-12.
EDG5A
EDG1A
0
0
2
2
EDG4B
EDG0B
0
0
1
1
EDG4A
EDG0A
0
0
0
0
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