MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 332

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
Read: Anytime
Write anytime for output compare function. Writes to these registers have no meaning or effect during
input capture.
All bits reset to zero.
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
7.3.2.15
Read: Anytime
Write: Anytime
All bits reset to zero.
332
Reset
Reset
Reset
PAEN
Field
6
W
W
W
R
R
R
Bit 15
Bit 7
Pulse Accumulator A System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable
1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded
16-Bit Pulse Accumulator A Control Register (PACTL)
15
0
0
0
0
7
7
bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled.
to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR have no effect.
Pulse Accumulator Input Edge Flag (PAIF) function is enabled. The PACA shares the input pin with IC7.
Figure 7-33. Timer Input Capture/Output Compare Register 7 High (TC7)
Figure 7-34. Timer Input Capture/Output Compare Register 7 Low (TC7)
= Unimplemented or Reserved
Figure 7-35. 16-Bit Pulse Accumulator Control Register (PACTL)
PAEN
Bit 14
Bit 6
14
0
0
0
6
6
Table 7-18. PACTL Field Descriptions
PAMOD
MC9S12XDP512 Data Sheet, Rev. 2.21
Bit 13
Bit 5
13
0
0
0
5
5
PEDGE
Bit 12
Bit 4
12
0
0
0
4
4
Description
Bit 11
CLK1
Bit 3
11
0
0
0
3
3
Bit 10
CLK0
Bit 2
10
0
0
0
2
2
Freescale Semiconductor
PAOVI
Bit 9
Bit 1
0
0
0
9
1
1
Bit 8
Bit 0
PAI
0
0
0
8
0
0