MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 345

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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7.3.2.27
Read: Anytime
Write: Anytime
All bits reset to zero.
Freescale Semiconductor
PTMPS7
Table 7-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 (continued)
Reset
PBOVI
PBEN
Field
0
0
0
0
0
1
6
1
W
R
Pulse Accumulator B System Enable — PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-bit pulse accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable bits
1 Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
Pulse Accumulator B Overflow Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PBOVF is set
16-Bit Pulse Accumulator B Control Register (PBCTL)
PTMPS6
0
0
7
in ICPAR are set.
the PACB 16-bit pulse accumulator B. When PACB is enabled, the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPAR have no effect.
The PACB shares the input pin with IC0.
0
0
0
0
1
1
Figure 7-49. 16-Bit Pulse Accumulator B Control Register (PBCTL)
= Unimplemented or Reserved
PBEN
PTMPS5
0
6
0
0
0
1
1
1
Table 7-35. PBCTL Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
PTMPS4
0
0
5
0
0
1
1
1
1
PTMPS3
0
0
4
0
1
1
1
1
1
Description
PTMPS2
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
0
0
3
1
1
1
1
1
1
PTMPS1
0
0
2
1
1
1
1
1
1
PTMPS0
PBOVI
0
1
1
1
1
1
1
1
Prescaler
Division
Rate
128
256
16
32
64
0
0
0
8
345

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