MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 430

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
10.3.2.5
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
430
Reset:
W
R
1
MSCAN Receiver Flag Register (CANRFLG)
WUPIF
This setting is not valid. Please refer to
TSEG13
Bit Time
1
0
7
This setting is not valid. Please refer to
0
0
0
0
1
1
:
TSEG22
0
0
1
1
:
Figure 10-8. MSCAN Receiver Flag Register (CANRFLG)
= Unimplemented
CSCIF
=
0
6
TSEG12
----------------------------------------------------- -
Prescaler value
0
0
0
0
1
1
:
f CANCLK
TSEG21
Table 10-7. Time Segment 2 Values
Table 10-8. Time Segment 1 Values
MC9S12XDP512 Data Sheet, Rev. 2.21
RSTAT1
0
0
1
1
:
0
5
TSEG11
0
0
1
1
1
1
:
Table 10-7
Table 10-35
TSEG20
RSTAT0
Table 10-35
0
4
0
1
0
1
:
1
TSEG10
+
and
TimeSegment1
0
1
0
1
0
1
:
for valid settings.
TSTAT1
Table
for valid settings.
3
0
Time Segment 2
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycle
10-8).
15 Tq clock cycles
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
Time segment 1
4 Tq clock cycles
1 Tq clock cycle
TSTAT0
:
0
2
+
TimeSegment2
:
1
Freescale Semiconductor
1
OVRIF
1
1
0
1
Eqn. 10-1
RXF
0
0

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