MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 502

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 11 Serial Communication Interface (S12SCIV5)
11.4.6
11.4.6.1
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
11.4.6.2
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
502
From TXD Pin
or Transmitter
SCRXD
LOOPS
RSRC
Receiver
Receiver Character Length
Character Reception
RXPOL
Control
SBR12:SBR0
Loop
Clock
Bus
Baud Divider
Figure 11-20. SCI Receiver Block Diagram
WAKE
RAF
RE
ILT
PE
PT
M
MC9S12XDP512 Data Sheet, Rev. 2.21
Recovery
Detect Logic
Data
Detect Logic
Active Edge
Break
BRKDFE
Checking
Wakeup
Parity
Logic
Internal Bus
H
RXEDGIE
RXEDGIF
BRKDIF
BRKDIE
8
11-Bit Receive Shift Register
RDRF
OR
7
SCI Data Register
6
5
4
NF
PE
FE
3
R8
IDLE
Freescale Semiconductor
ILIE
RIE
2
Break IRQ
RX Active Edge IRQ
1
0
L
RWU
RDRF/OR
Idle IRQ
IRQ