MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 526

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAAR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 12 Serial Peripheral Interface (S12SPIV4)
12.3.2.5
Read: Anytime; normally read only when SPIF is set
Write: Anytime
526
Reset
W
R
The SPI data register is both the input and output register for SPI data. A write to this register
allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data
byte is transmitted immediately after the previous transmission has completed. The SPI transmitter
empty flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new
data.
Received data in the SPIDR is valid when SPIF is set.
If SPIF is cleared and a byte has been received, the received byte is transferred from the receive
shift register to the SPIDR and SPIF is set.
If SPIF is set and not serviced, and a second byte has been received, the second received byte is
kept as valid byte in the receive shift register until the start of another transmission. The byte in the
SPIDR does not change.
If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced before the start of
a third transmission, the byte in the receive shift register is transferred into the SPIDR and SPIF
remains set (see
If SPIF is set and a valid byte is in the receive shift register, and SPIF is serviced after the start of
a third transmission, the byte in the receive shift register has become invalid and is not transferred
into the SPIDR (see
Bit 7
SPI Data Register (SPIDR)
0
7
Figure
6
0
6
Figure
12-8).
Figure 12-7. SPI Data Register (SPIDR)
12-9).
MC9S12XDP512 Data Sheet, Rev. 2.21
5
0
5
4
0
4
3
0
3
2
0
2
Freescale Semiconductor
2
0
1
Bit 0
0
0

Related parts for MC9S12XDT256CAA