MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 565

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.4.2.2
In Reduced Power Mode, the gate of the output transistor is connected directly to a reference voltage to
reduce power consumption.
14.4.3
Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input
voltage (V
status flag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode
or Shutdown Mode.
14.4.4
This functional block monitors V
the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the power-on
sequence.
14.4.5
Block LVR monitors the primary output voltage V
LVR asserts; if V
is available only in Full Performance Mode.
14.4.6
This part contains the register block of VREG_3V3 and further digital functionality needed to control the
operating modes. CTRL also represents the interface to the digital core logic.
14.4.7
Subblock API can generate periodical interrupts independent of the clock source of the MCU. To enable
the timer, the bit APIFE needs to be set.
The API timer is either clocked by a trimmable internal RC oscillator or the bus clock. Timer operation
will freeze when MCU clock source is selected and bus clock is turned off. See CRG specification for
details. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is
not set.
The APIR[11:0] bits determine the interrupt period. APIR[11:0] can only be written when APIFE is
cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[11:0] bits. When
the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered
if interrupt enable bit APIE = 1. The timer is started automatically again after it has set APIF.
The procedure to change APICLK or APIR[11:0] is first to clear APIFE, then write to APICLK or
APIR[11:0], and afterwards set APIFE.
Freescale Semiconductor
DDA
Low-Voltage Detect (LVD)
Power-On Reset (POR)
Low-Voltage Reset (LVR)
Regulator Control (CTRL)
Autonomous Periodical Interrupt (API)
Reduced Power Mode
–V
DD
SSA
rises above the deassertion level (V
) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever
DD
MC9S12XDP512 Data Sheet, Rev. 2.21
. If V
DD
is below V
DD
. If it drops below the assertion level (V
PORD
LVRD
, POR is asserted; if V
) signal, LVR deasserts. The LVR function
Chapter 14 Voltage Regulator (S12VREG3V3V5)
DD
exceeds V
LVRA
) signal,
PORD
565
,