MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 576

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 15 Background Debug Module (S12XBDMV2)
15.3.2.2
Register Global Address 0x7FFF06
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte
of the condition code register of the user’s program. It is also used for temporary storage in the standard
BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
576
Special Single-Chip Mode
PLLSEL
0
0
1
1
All Other Modes
CLKSW
BDM CCR LOW Holding Register (BDMCCRL)
0
1
0
1
When BDM is made active, the CPU stores the content of its CCR
in the BDMCCRL register. However, out of special single-chip reset, the
BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the
CCR
BDMCCRL register is read zero.
Reset
Bus clock dependent on oscillator
Bus clock dependent on oscillator
Alternate clock (refer to the device specification to determine the alternate clock source)
Bus clock dependent on the PLL
L
W
R
register in this CPU mode. Out of reset in all other modes the
Figure 15-4. BDM CCR LOW Holding Register (BDMCCRL)
CCR7
1
0
7
MC9S12XDP512 Data Sheet, Rev. 2.21
CCR6
Table 15-3. BDM Clock Sources
1
0
6
CCR5
0
0
5
NOTE
CCR4
BDMCLK
0
0
4
CCR3
1
0
3
CCR2
0
0
2
L
register
Freescale Semiconductor
CCR1
1
0
0
CCR0
0
0
0