MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 577

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3.2.3
Register Global Address 0x7FFF07
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR HIGH holding register is used to save the high
byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be
written to modify the CCR value.
15.3.2.4
Register Global Address 0x7FFF08
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
15.3.3
The family ID is a 8-bit value located in the firmware ROM (at global address: 0x7FFF0F). The read-only
value is a unique family ID which is 0xC1 for S12X devices.
Freescale Semiconductor
BGP[6:0]
Reset
Reset
BGAE
Field
6–0
7
W
W
R
R
BGAE
Family ID Assignment
BDM Global Page Access Enable Bit — BGAE enables global page access for BDM hardware and firmware
read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD_ and
WRITE_BD_) can not be used for global accesses even if the BGAE bit is set.
0 BDM Global Access disabled
1 BDM Global Access enabled
BDM Global Page Index Bits 6–0 — These bits define the extended address bits from 22 to 16. For more
detailed information regarding the global page window scheme, please refer to the S12X_MMC Block Guide.
BDM CCR HIGH Holding Register (BDMCCRH)
BDM Global Page Index Register (BDMGPR)
7
0
0
7
0
= Unimplemented or Reserved
Figure 15-5. BDM CCR HIGH Holding Register (BDMCCRH)
BGP6
0
0
6
0
6
Figure 15-6. BDM Global Page Register (BDMGPR)
Table 15-4. BDMGPR Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
BGP5
0
0
5
0
5
BGP4
0
0
4
0
4
Description
BGP3
0
0
3
0
3
Chapter 15 Background Debug Module (S12XBDMV2)
CCR10
BGP2
2
0
2
0
CCR9
BGP1
0
1
0
1
CCR8
BGP0
0
0
0
0
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