MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 609

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the
CPU will default to that of the spurious interrupt vector.
16.4.5
The XINT supports three system reset exception request types (please refer to CRG for details):
16.4.6
The priority (from highest to lowest) and address of all exception vectors issued by the XINT upon request
by the CPU is shown in
1
Freescale Semiconductor
(Vector base + 0x00F0–0x0012) Device specific I bit maskable interrupt sources (priority determined by the associated
16 bits vector address based
1. Pin reset, power-on reset, low-voltage reset, or illegal address reset
2. Clock monitor reset request
3. COP watchdog reset request
(Vector base + 0x00F8)
(Vector base + 0x00F6)
(Vector base + 0x00F4)
(Vector base + 0x00F2)
(Vector base + 0x0010)
Vector Address
0xFFFE
0xFFFC
0xFFFA
Reset Exception Requests
Exception Priority
Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0010)).
1
Table
Pin reset, power-on reset, low-voltage reset, illegal address reset
Clock monitor reset
COP watchdog reset
Unimplemented opcode trap
Software interrupt instruction (SWI) or BDM vector request
XIRQ interrupt request
IRQ interrupt request
configuration registers, in descending order)
Spurious interrupt
Table 16-8. Exception Vector Map and Priority
16-8.
MC9S12XDP512 Data Sheet, Rev. 2.21
NOTE
Source
Chapter 16 Interrupt (S12XINTV1)
609

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