MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 617

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.2
17.3.2.1
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data is read from this register.
Write: Anytime. In emulation modes write operations will also be directed to the external bus.
Freescale Semiconductor
Address
Address: 0x000A PRR
1. ROMON is bit[0] of the register MMCTL1 (see
0x011C
0x011D
0x011E
0x011F
Reset
1
2
W
R
CS3E, CS2E, CS1E, CS0E
Disabled: feature always inactive.
Enabled: activity is controlled by the appropriate register bit value.
RAMWPC
RAMXGU
RAMSHU
RAMSHL
Register
Register Descriptions
Name
MMC Control Register (MMCCTL0)
Register Bit
0
0
7
= Unimplemented or Reserved
W
W
W
W
R
R
R
R
0
0
6
RPWE
Bit 7
1
1
1
Figure 17-3. MMC Control Register (MMCCTL0)
Table 17-3. Chip Selects Function Activity
Disabled
Figure 17-2. MMC Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
= Unimplemented or Reserved
NS
XGU6
SHU6
SHL6
0
0
5
6
0
Figure
1
Disabled
1-10)
XGU5
SHU5
SHL5
SS
5
0
0
0
4
Enabled
XGU4
SHU4
SHL4
NX
4
0
CS3E
Chip Modes
0
3
2
Chapter 17 Memory Mapping Control (S12XMMCV2)
XGU3
SHU3
SHL3
Disabled
3
0
ES
CS2E
0
2
XGU2
SHU2
SHL2
Enabled
2
0
EX
CS1E
0
1
XGU1
SHU1
SHL1
AVIE
1
Enabled
ST
ROMON
CS0E
XGU0
SHU0
SHL0
Bit 0
AVIF
0
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1