MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 653

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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18.1.3
The S12X architecture implements a number of memory mapping schemes including
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
18.1.4
This subsection lists and briefly describes all operating modes supported by the MMC.
18.1.4.1
1. Resources are also called targets.
Freescale Semiconductor
Simultaneous accesses to different resources
Resolution of target bus access collision
Access restriction control from masters to some targets (e.g., RAM write access protection for user
specified areas)
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU, BDM and XGATE
ROM control bits to enable the on-chip FLASH or ROM selection
Port replacement registers access control
Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
a CPU 8 MByte global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
a BDM 8 MByte global map, defined using a global page (BDMGPR) register and dedicated 23-bit
address load/store instructions.
a (CPU or BDM) 64 KByte local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64 KBytes visible at any instant can be
considered as the local map accessed by the 16-bit (CPU or BDM) address.
The XGATE 64 Kbyte local map.
Run mode
MMC is functional during normal run mode.
Wait mode
MMC is functional during wait mode.
Stop mode
MMC is inactive during stop mode.
S12X Memory Mapping
Modes of Operation
Power Saving Modes
MC9S12XDP512 Data Sheet, Rev. 2.21
1
(internal, external, and peripherals) (see )
Chapter 18 Memory Mapping Control (S12XMMCV3)
653

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