MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 669

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.2.10 RAM XGATE Upper Boundary Register (RAMXGU)
Read: Anytime
Write: Anytime when RWPE = 0
18.3.2.11 RAM Shared Region Lower Boundary Register (RAMSHL)
Read: Anytime
Write: Anytime when RWPE = 0
Freescale Semiconductor
Address: 0x011D
Address: 0x011E
XGU[6:0]
SHL[6:0]
Reset
Reset
Field
Field
6–0
6–0
W
W
R
R
XGATE Region Upper Boundary Bits 6-0 — These bits define the upper boundary of the RAM region allocated
to the XGATE module in multiples of 256 bytes. The 256 byte block selected by this register is included in the
region. See
RAM Shared Region Lower Boundary Bits 6–0 — These bits define the lower boundary of the shared memory
region in multiples of 256 bytes. The block selected by this register is included in the region. See
for details.
1
1
1
1
7
7
Figure 18-19. RAM Shared Region Lower Boundary Register (RAMSHL)
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 18-18. RAM XGATE Upper Boundary Register (RAMXGU)
Figure 18-25
XGU6
SHL6
1
1
6
6
Table 18-16. RAMXGU Field Descriptions
Table 18-17. RAMSHL Field Descriptions
for details.
MC9S12XDP512 Data Sheet, Rev. 2.21
XGU5
SHL5
1
1
5
5
XGU4
SHL4
1
1
4
4
Description
Description
XGU3
SHL3
1
1
3
3
Chapter 18 Memory Mapping Control (S12XMMCV3)
XGU2
SHL2
1
1
2
2
XGU1
SHL1
1
1
1
1
Figure 18-25
XGU0
SHL0
1
1
0
0
669