MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 698

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.2
Read: Anytime
Write: Never
700
0x0021
SSF[2:0}
Reset
EXTF
POR
Field
TBF
2–0
7
6
W
R
TBF
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].
The TBF bit is cleared when ARM in DBGC1 is written to a 1. The TBF is cleared by the power on reset
initialization. Other system generated resets have no affect on this bit
External Tag Hit Flag — The EXTF bit indicates if a tag hit condition from an external TAGHI/TAGLO tag was
met since arming. This bit is cleared when ARM in DBGC1 is written to a 1.
0 External tag hit has not occurred
1 External tag hit has occurred
State Sequencer Flag Bits — The SSF bits indicate in which state the state sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by a breakpoint, then the state sequencer returns to state0 and
these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See
Debug Status Register (DBGSR)
0
7
COMRV
Unimplemented or Reserved
01
10
11
EXTF
Table 19-7. SSF[2:0] — State Sequence Flag Bit Encoding
0
0
6
101,110,111
Figure 19-4. Debug Status Register (DBGSR)
SSF[2:0]
Visible Comparator
000
001
010
011
100
Table 19-6. DBGSR Field Descriptions
Comparator B
Comparator C
Comparator D
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 19-5. COMRV Encoding
0
0
0
5
0
0
0
4
Description
Visible State Control Register
State0 (disarmed)
Current State
Final State
Reserved
0
0
0
3
State1
State2
State3
DBGSCR2
DBGSCR3
DBGSCR3
SSF2
0
0
2
Table
19-7.
Freescale Semiconductor
SSF1
0
0
1
SSF0
0
0
0

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