MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 704

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAAR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.9
Read: Anytime
Write: Anytime when DBG not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state while in State2. The matches refer to the match channels of the comparator match
control logic as depicted in
Register
associated DBGXCTL control register.
706
SC[3:0]
0x0027
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
W
R
(DBGXCTL)”. Comparators must be enabled by setting the comparator enable bit in the
Debug State Control Register 2 (DBGSCR2)
0
0
7
Match3 triggers to State3....... Match1 triggers to final state....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers final state....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers final state....... Other matches have no effect
Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
Unimplemented or Reserved
Figure 19-11. Debug State Control Register 2 (DBGSCR2)
0
0
6
Figure 19-1
Table 19-21. State1 Sequencer Next Sate Selection
Match2 triggers to final state....... Other matches have no effect
Match2 triggers to State2....... Other matches have no effect
Match2 triggers to State3....... Other matches have no effect
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
and described in
Any match triggers to final state
Any match triggers to state2
Any match triggers to state3
0
0
4
Description
Reserved
Reserved
Reserved
Reserved
Section 19.3.1.11.1, “Debug Comparator Control
SC3
0
3
SC2
0
2
Freescale Semiconductor
SC1
0
1
SC0
0
0

Related parts for MC9S12XDT256CAA