MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 705

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3.1.10 Debug State Control Register 3 (DBGSCR3)
Read: Anytime
Write: Anytime when DBG not armed.
This register is visible at 0x0027 only with COMRV[1]=1. The state control register 3 selects the targeted
next state while in State3. The matches refer to the match channels of the comparator match control logic
as depicted in
Freescale Semiconductor
SC[3:0]
0x0027
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SC[3:0}
Reset
Field
3–0
W
R
State Control Bits — These bits select the targeted next state while in State2, based upon the match event.
See
The trigger priorities described in
the lower channel number ([0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final
state has priority over all other matches.
0
0
7
Figure 19-1
Table
Match1 triggers to State3....... Match0 triggers final state....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers final state....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers final state....... Other matches have no effect
Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect
Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect
Unimplemented or Reserved
19-23.
Figure 19-12. Debug State Control Register 3 (DBGSCR3)
0
0
6
and described in
Table 19-23. State2 Sequencer Next State Selection
Match3 triggers to final state....... Other matches have no effect
Table 19-22. DBGSCR2 Field Descriptions
Match3 triggers to State1....... Other matches have no effect
Match3 triggers to State3....... Other matches have no effect
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
Table 19-38
Section 19.3.1.11.1, “Debug Comparator Control Register
Any match triggers to final state
Any match triggers to state1
Any match triggers to state3
0
0
4
dictate that in the case of simultaneous matches, the match on
Description
Reserved
Reserved
Reserved
Reserved
Description
SC3
0
3
Chapter 19 S12X Debug (S12XDBGV2) Module
SC2
0
2
SC1
0
1
SC0
0
0
707