MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 708

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 19 S12X Debug (S12XDBGV2) Module
Table 19-28
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus, these bits are ignored if tagged triggering is selected.
710
(COMP B/D)
COMPE
Field
RWE
BRK
SRC
TAG
RW
SZ
6
5
4
3
2
1
0
shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
This bit position has NDB functionality for comparators A and C
0 Word access size will be compared
1 Byte access size will be compared
Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the
matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.
0 Trigger immediately on match
1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated
Break — This bit controls whether a comparator match can cause an immediate breakpoint independent of state
sequencer state. The module breakpoints must be enabled using the DBGC1 bits DBGBRK[1:0].
0 Breakpoints may only be generated from this channel when the state machine reaches final state.
1 A match on this channel generates an immediate breakpoint, tracing, if active, is terminated and the module
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator. The RW bit is not used if RWE = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated
comparator. This bit is not useful for tagged operations.
1 Read/Write is used in comparison
0 Read/Write is not used in comparison
SRC — Determines mapping of comparator to CPU or XGATE
0 The comparator is mapped to CPU busses
1 The comparator is mapped to XGATE address and data busses
Comparator Enable Bit— Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
RWE Bit
disarmed.
0
0
1
1
1
1
Table 19-27. DBGXCTL Field Descriptions (continued)
Table 19-28. Read or Write Comparison Logic Table
RW Bit
0
0
1
1
x
x
MC9S12XDP512 Data Sheet, Rev. 2.21
RW Signal
0
1
0
1
0
1
Description
RW not used in comparison
RW not used in comparison
Write data bus
Read data bus
Comment
No match
No match
Freescale Semiconductor

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