MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 717

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.4.3.4
The XGATE S/W breakpoint request issues a forced breakpoint request to the CPU immediately
independent of DBG settings. If the debug module is armed triggers the state sequencer into the disarmed
state. Active tracing sessions are terminated immediately, thus if tracing has not yet begun using begin-
trigger, no trace information is stored. XGATE generated breakpoints are independent of the DBGBRK
bits. The XGSBPE bit in DBGC1 determines if the XGATE S/W breakpoint function is enabled. The BDM
bit in DBGC1 determines if the XGATE requested breakpoint causes the system to enter BDM mode or
initiate a software interrupt (SWI).
19.4.3.5
At any time independent of comparator matches or external tag signals it is possible to initiate a tracing
session and/or breakpoint by writing to the TRIG bit in DBGC1. This triggers the state sequencer into the
final state and issues a forced breakpoint request to both CPU and XGATE.
19.4.3.6
In case of simultaneous triggers, the priority is resolved according to
trigger is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a
trigger of a higher priority. The trigger priorities described in
simultaneous matches, the match on the lower channel number ([0,1,2,3) has priority. The SC[3:0]
encoding ensures that a match leading to final state has priority over all other matches independent of
current state sequencer state. When configured for range modes a simultaneous match of comparators A
and C generates an active match0 while match2 is suppressed.
Freescale Semiconductor
Priority
Highest
Lowest
Match0 (force or tag hit)
Match1 (force or tag hit)
Match2 (force or tag hit)
Match3 (force or tag hit)
External TAGHI/TAGLO
Trigger On XGATE S/W Breakpoint Request
Immediate Trigger
Trigger Priorities
Source
XGATE
TRIG
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 19-38. Trigger Priorities
Immediate forced breakpoint......(Tracing terminated immediately).
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Table 19-38
Enter final state
Enter State0
Action
Chapter 19 S12X Debug (S12XDBGV2) Module
Table
dictate that in the case of
19-38. The lower priority
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