MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 751

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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20.3.2.3
Read: Anytime
Write: Bits 7:6 only when S12XDBG is neither secure nor armed.
Freescale Semiconductor
Address: 0x0022
TSOURCE
TRCMOD
TRANGE
TALIGN
Reset
Field
7–6
5–4
3–2
1–0
W
R
Bits 5:0 anytime the module is disarmed.
Trace Source Control Bits — The TSOURCE bits select the data source for the tracing session. If the MCU
system is secured, these bits cannot be set and tracing is inhibited. See
Trace Range Bits — The TRANGE bits allow filtering of trace information from a selected address range when
tracing from the S12XCPU in Detail Mode. The XGATE tracing range cannot be narrowed using these bits. To
use a comparator for range filtering, the corresponding COMPE and SRC bits must remain cleared. If the
COMPE bit is not clear then the comparator will also be used to generate state sequence triggers. If the
corresponding SRC bit is set the comparator is mapped to the XGATE buses, the TRANGE bits have no effect
on the valid address range, memory accesses within the whole memory map are traced. See
Trace Mode Bits — See
information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See
Table
Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a
tracing session. See
Debug Trace Control Register (DBGTCR)
0
7
1
2
TSOURCE
No range limitations are allowed. Thus tracing operates as if TRANGE = 00.
No Detail Mode tracing supported. If TRCMOD = 10, no information is stored.
20-11.
TSOURCE
11
10
00
01
1,2
1
0
6
Figure 20-5. Debug Trace Control Register (DBGTCR)
Table 20-9. TSOURCE — Trace Source Bit Encoding
Table
Table 20-8. DBGTCR Field Descriptions
Section 20.4.5.2
20-12.
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
TRANGE
for detailed Trace Mode descriptions. In Normal Mode, change of flow
Both S12XCPU and XGATE
0
4
No tracing requested
Tracing Source
Description
S12XCPU
XGATE
0
3
TRCMOD
Chapter 20 S12X Debug (S12XDBGV3) Module
Table
0
2
20-9.
0
1
TALIGN
Table
20-10.
0
0
753

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