MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 759

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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20.3.2.7.3
Read: Anytime
Write: Anytime when S12XDBG not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in
enabled by setting the comparator enable bit in the associated DBGXCTL control register.
The trigger priorities described in
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
Freescale Semiconductor
Address: 0x0027
SC[3:0]
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
Field
3–0
W
R
These bits select the targeted next state whilst in State3, based upon the match event.
0
0
7
Debug State Control Register 3 (DBGSCR3)
Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect
Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect
= Unimplemented or Reserved
Figure 20-11. Debug State Control Register 3 (DBGSCR3)
0
0
Table 20-25. State3 — Sequencer Next State Selection
6
Figure 20-1
Match1 triggers to Final State....... Other matches have no effect
Match2 triggers to Final State....... Other matches have no effect
Match3 triggers to Final State....... Other matches have no effect
Table 20-24. DBGSCR3 Field Descriptions
Match0 triggers to State1....... Other matches have no effect
Match1 triggers to State1....... Other matches have no effect
Match0 triggers to State2....... Other matches have no effect
Match0 triggers to Final State.......Match1 triggers to State1
Match1 triggers to State2....... Other matches have no effect
Table 20-38
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
and described in
Any match triggers to Final State
Any match triggers to state1
Any match triggers to state2
dictate that in the case of simultaneous matches, the match
0
0
4
Description
Description
Reserved
Reserved
Section
SC3
0
3
20.3.2.8.1”. Comparators must be
Chapter 20 S12X Debug (S12XDBGV3) Module
SC2
0
2
SC1
0
1
SC0
0
0
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