MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 782

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 20 S12X Debug (S12XDBGV3) Module
upon the state of the DBGBRK or ARM bits in DBGC1. They depend solely on the state of the XGSBPE
and BDM bits. Thus it is not necessary to ARM the DBG module to use XGATE software breakpoints to
generate breakpoints in the S12XCPU program flow, but it is necessary to set XGSBPE. Furthermore, if a
breakpoint to BDM is required, the BDM bit must also be set. When the XGATE requests an S12XCPU
breakpoint, the XGATE program flow stops by default, independent of the S12XDBG module.
20.4.7.2
Breakpoints can be generated when internal comparator channels trigger the state sequencer to the Final
State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the
execution stage of the instruction queue.
If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing session
has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on
completion of the subsequent trace (see
requested immediately.
If the BRK bit is set on the triggering channel, then the breakpoint is generated immediately independent
of tracing trigger alignment.
20.4.7.3
If a TRIG triggers occur, the Final State is entered. Tracing trigger alignment is defined by the TALIGN
bits. If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing
session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only
on completion of the subsequent trace (see
requested immediately. TRIG breakpoints are possible even if the S12XDBG module is disarmed.
784
BRK
0
0
0
0
0
0
1
1
x
Breakpoints From Internal Comparator Channel Final State Triggers
Breakpoints Generated Via The TRIG Bit
Table 20-44. Breakpoint Setup For Both XGATE and S12XCPU Breakpoints
00,01,10
00,01,10
TALIGN
00
00
01
01
10
10
11
DBGBRK[n]
0
1
0
1
0
1
1
0
x
MC9S12XDP512 Data Sheet, Rev. 2.21
Table
Table
20-44). If no tracing session is selected, breakpoints are
Terminate tracing and generate breakpoint immediately on trigger
Fill Trace Buffer until trigger, then breakpoint request occurs
20-44). If no tracing session is selected, breakpoints are
Request breakpoint after the 32 further Trace Buffer entries
Store a further 32 Trace Buffer line entries after trigger
Store a further 32 Trace Buffer line entries after trigger
A breakpoint request occurs when Trace Buffer is full
Terminate tracing immediately on trigger
(no breakpoints — keep running)
(no breakpoints — keep running)
(no breakpoints — keep running)
Fill Trace Buffer until trigger
Start Trace Buffer at trigger
Start Trace Buffer at trigger
Breakpoint Alignment
Reserved
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