MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 82

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.2
This section lists and describes the signals that connect off chip.
2.2.1
These pins provide operating voltage (V
the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required, V
and V
2.2.2
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter
that eliminates the VCO input ripple. The value of the external filter network and the reference frequency
determines the speed of the corrections and the stability of the PLL. Refer to the device specification for
calculation of PLL Loop Filter (XFC) components. If PLL usage is not required, the XFC pin must be tied
to V
2.2.3
RESET is an active low bidirectional reset pin. As an input. it initializes the MCU asynchronously to a
known start-up state. As an open-drain output, it indicates that a system reset (internal to the MCU) has
been triggered.
2.3
This section provides a detailed description of all registers accessible in the CRG.
82
DDPLL
SSPLL
External Signal Description
Memory Map and Register Definition
.
V
XFC — External Loop Filter Pin
RESET — Reset Pin
must be connected to properly.
DDPLL
and V
SSPLL
Figure 2-2. PLL Loop Filter Connections
MC9S12XDP512 Data Sheet, Rev. 2.21
MCU
— Operating and Ground Voltage Pins
DDPLL
XFC
) and ground (V
R
C
S
S
SSPLL
C
P
V
DDPLL
) for the PLL circuitry. This allows
Freescale Semiconductor
DDPLL

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