MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 825

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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22.3.2.1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
22.3.2.2
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Freescale Semiconductor
Function
Function
PA[7:0]
Reset
Reset
Field
7–0
Alt.
Alt.
W
W
R
R
ADDR15
ADDR7
IVD15
IVD7
Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively in
expanded modes. When this port is not used for external addresses, these pins can be used as general purpose
I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
PA7
mux
PB7
mux
Port A Data Register (PORTA)
Port B Data Register (PORTB)
0
0
7
7
ADDR14
ADDR6
IVD14
IVD6
mux
PB6
mux
PA6
0
0
6
6
Figure 22-4. Port B Data Register (PORTB)
Figure 22-3. Port A Data Register (PORTA)
Table 22-4. PORTA Field Descriptions
ADDR13
ADDR5
MC9S12XDP512 Data Sheet, Rev. 2.21
IVD13
IVD5
PB5
PA5
mux
mux
0
0
5
5
ADDR12
ADDR4
IVD12
IVD4
mux
PB4
mux
PA4
0
0
4
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
ADDR11
ADDR3
IVD11
IVD3
PB3
PA3
mux
mux
0
0
3
3
ADDR10
ADDR2
IVD10
IVD2
mux
PB2
mux
PA2
0
0
2
2
ADDR9
ADDR1
IVD9
IVD1
PB1
PA1
mux
mux
0
0
1
1
ADDR8
ADDR0
IVD8
IVD0
UDS
mux
PB0
mux
PA0
or
0
0
0
0
827

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