MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 85

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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2.3.2.1
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (f
Read: Anytime
Write: Anytime except if PLLSEL = 1
2.3.2.2
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference
divider divides OSCCLK frequency by REFDV + 1.
Read: Anytime
Write: Anytime except when PLLSEL = 1
Freescale Semiconductor
Reset
Reset
W
W
R
R
PLLCLK
CRG Synthesizer Register (SYNR)
CRG Reference Divider Register (REFDV)
0
0
0
0
7
7
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
Write to this register initializes the lock detector bit and the track detector
bit.
Write to this register initializes the lock detector bit and the track detector
bit.
=
2xOSCCLKx
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 2-5. CRG Reference Divider Register (REFDV)
Figure 2-4. CRG Synthesizer Register (SYNR)
----------------------------------- -
REFDV
SYNR
REFDV5
MC9S12XDP512 Data Sheet, Rev. 2.21
SYN5
0
0
5
5
+
+
1
1
REFDV4
SYN4
NOTE
NOTE
NOTE
0
0
4
4
REFDV3
SYN3
0
0
3
3
Chapter 2 Clocks and Reset Generator (S12CRGV6)
REFDV2
SYN2
0
0
2
2
SCM
REFDV1
SYN1
).
0
0
1
1
REFDV0
SYN0
0
0
0
0
85

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