MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 873

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.2.64 Port AD0 Reduced Drive Register 1 (RDR1AD0)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each output pin PAD[07:00] as either full or reduced. If the
port is used as input this bit is ignored.
22.3.2.65 Port AD0 Pull Up Enable Register 1 (PER1AD0)
Read: Anytime.
Write: Anytime.
This register activates a pull-up device on the respective pin PAD[07:00] if the port is used as input. This
bit has no effect if the port is used as output. Out of reset no pull device is enabled.
Freescale Semiconductor
RDR1AD0[7:0]
PER1AD0[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
RDR1AD07
PER1AD07
0
0
7
7
Reduced Drive Port AD0 Register 1
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
Pull Device Enable Port AD0 Register 1
0 Pull-up device is disabled.
1 Pull-up device is enabled.
RDR1AD06
PER1AD06
Figure 22-66. Port AD0 Reduced Drive Register 1 (RDR1AD0)
Figure 22-67. Port AD0 Pull Up Enable Register 1 (PER1AD0)
0
0
6
6
Table 22-59. RDR1AD0 Field Descriptions
Table 22-60. PER1AD0 Field Descriptions
RDR1AD05
PER1AD05
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
RDR1AD04
PER1AD04
0
0
4
4
Description
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
RDR1AD03
PER1AD03
0
0
3
3
RDR1AD02
PER1AD02
0
0
2
2
RDR1AD01
PER1AD01
0
0
1
1
RDR1AD00
PER1AD00
0
0
0
0
875