MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 879
MC9S12XDT256CAA
Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XDT256CAA
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XDT256CAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S12XDT256CAAR
Manufacturer:
Freescale Semiconductor
Quantity:
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22.4
Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an
output from the external bus interface module or a peripheral module or an input to the external bus
interface module or a peripheral module.
A set of configuration registers is common to all ports with exceptions in the expanded bus interface and
ATD ports
not become active.
This device does not become active while the port is used as a push-pull output.
1
22.4.1
22.4.1.1
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration
Freescale Semiconductor
Port
AD0
AD1
Each cell represents one register with individual configuration bits
M
A
B
C
D
E
K
S
P
H
T
J
Example: Selecting a pull-up device
Functional Description
Data
(Table
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Registers
Data Register
22-67). All registers can be written at any time; however a specific configuration might
Direction
Data
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Table 22-67. Register Availability per Port
Input
yes
yes
yes
yes
yes
yes
—
—
—
—
—
—
—
—
MC9S12XDP512 Data Sheet, Rev. 2.21
Reduced
(Figure
Drive
yes
yes
yes
yes
yes
yes
yes
yes
yes
22-76).
Enable
Pull
yes
yes
yes
yes
yes
yes
yes
yes
yes
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
Polarity
Select
yes
yes
yes
yes
yes
—
—
—
—
—
—
—
—
—
1
Wired-OR
Mode
yes
yes
—
—
—
—
—
—
—
—
—
—
—
—
Interrupt
Enable
yes
yes
yes
—
—
—
—
—
—
—
—
—
—
—
Interrupt
Flag
yes
yes
yes
—
—
—
—
—
—
—
—
—
—
—
881
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