MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 923

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAAR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
DDRE[7:2]
PE[7:0]
Reset
Field
23.0.5.10 Port E Data Direction Register (DDRE)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in
all other modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Field
7–0
7–0
W
R
DDRE7
Port E — Port E bits 7–0 are associated with external bus control signals and interrupt inputs. These include
mode select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (TAGHI,
TAGLO), Read/Write (R/W), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS), IRQ, and XIRQ.
When not used for any of these specific functions, Port E pins 7–2 can be used as general purpose I/O and
pins 1–0 can be used as general purpose inputs.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low.
Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.
Data Direction Port E — his register controls the data direction for port E. When Port E is operating as a general
purpose I/O port, DDRE determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits
1 and 0, can be read regardless of whether the alternate interrupt function is enabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
7
0
on PORTE after changing the DDRE register.
= Unimplemented or Reserved
DDRE6
0
6
Figure 23-12. Port E Data Direction Register (DDRE)
Table 23-12. PORTE Field Descriptions
Table 23-13. DDRE Field Descriptions
DDRE5
5
0
DDRE4
0
4
Description
Description
DDRE3
3
0
DDRE2
0
2
1
0
0
0
0
0

Related parts for MC9S12XDT256CAA