MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 941

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset
Reset
PWM
23.0.5.38 Port P Data Register (PTP)
Read: Anytime.
Write: Anytime.
Port P pins 7–0 are associated with the PWM as well as the SPI1 and SPI2. These pins can be used
as general purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value
of the port register, otherwise the buffered pin input state is read.
The PWM function takes precedence over the general purpose I/O and the SPI2 or SPI1 function
if the associated PWM channel is enabled. While channels 6-0 are output only if the respective
channel is enabled, channel 7 can be PWM output or input if the shutdown feature is enabled. Refer
to PWM section for details.
The SPI2 function takes precedence over the general purpose I/O function if enabled. Refer to SPI
section for details. The SPI1 function takes precedence over the general purpose I/O function if
enabled. Refer to SPI section for details.
23.0.5.39 Port P Input Register (PTIP)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to
detect overload or short circuit conditions on output pins.
SPI
W
W
associated pin values.
R
R
1
PWM7
PTIP7
SCK2
PTP7
—
7
0
7
= Unimplemented or Reserved
PWM6
PTIP6
PTP6
SS2
—
0
6
6
Figure 23-41. Port P Input Register (PTIP)
Figure 23-40. Port P Data Register (PTP)
MOSI2
PWM5
PTIP5
PTP5
—
5
0
5
MISO2
PWM4
PTIP4
PTP4
—
0
4
4
PWM3
PTIP3
PTP3
SS1
—
3
0
3
PWM2
PTIP2
SCK1
PTP2
—
0
2
2
MOSI1
PWM1
PTIP1
PTP1
—
1
0
1
MISO1
PWM0
PTIP0
PTP0
—
0
0
0