MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 942

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAAR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.40 Port P Data Direction Register (DDRP)
Read: Anytime.
Write: Anytime.
This register configures each port P pin as either input or output.
If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–0
channel. Channel 7 can force the pin to input if the shutdown feature is enabled. Refer to PWM section for
details.
If SPI is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRP bits revert to controlling the I/O direction of a pin when the associated peripherals are disabled.
23.0.5.41 Port P Reduced Drive Register (RDRP)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port P output pin as either full or reduced. If the port is
used as input this bit is ignored.
944
DDRP[7:0]
Reset
Reset
Field
7–0
W
W
R
R
DDRP7
RDRP7
Data Direction Port P
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
0
7
7
on PTP or PTIP registers, when changing the DDRP register.
DDRP6
RDRP6
0
0
6
6
Figure 23-43. Port P Reduced Drive Register (RDRP)
Figure 23-42. Port P Data Direction Register (DDRP)
Table 23-39. DDRP Field Descriptions
DDRP5
RDRP5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
DDRP4
RDRP4
0
0
4
4
Description
DDRP3
RDRP3
0
0
3
3
DDRP2
RDRP2
0
0
2
2
DDRP1
RDRP1
Freescale Semiconductor
0
0
1
1
DDRP0
RDRP0
0
0
0
0

Related parts for MC9S12XDT256CAA