MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 95

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Freescale Semiconductor
WRTMASK
CR[1:0]
Field
2–0
5
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits
while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of
WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL
1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL. (Does not count for “write once”.)
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see
time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the
COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be
avoided by periodically (before time-out) reinitializing the COP counter via the ARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at
highest time-out period (
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in emulation or special modes
1
OSCCLK cycles are referenced from the previous COP time-out reset
(writing 0x_55/0x_AA to the ARMCOP register)
CR2
Table 2-9. COPCTL Field Descriptions (continued)
0
0
0
0
1
1
1
1
2
24
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 2-10. COP Watchdog Rates
cycles) in normal COP mode (Window COP mode disabled):
CR1
0
0
1
1
0
0
1
1
CR0
0
1
0
1
0
1
0
1
Description
Cycles to Time-out
Chapter 2 Clocks and Reset Generator (S12CRGV6)
COP disabled
OSCCLK
1
2
2
2
2
2
2
2
14
16
18
20
22
23
24
Table
2-10). The COP
95

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