MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 953

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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PERJ[7:4]
PERJ[2:0]
PPSJ[7:4]
PPSJ[2:0]
Reset
Reset
This register configures whether a pull-up or a pull-down device is activated, if the port is used as
input or as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of
reset a pull-up device is enabled.
Field
23.0.5.59 Port J Polarity Select Register (PPSJ)
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as
selecting a pull-up or pull-down device if enabled.
Field
23.0.5.60 Port J Interrupt Enable Register (PIEJ)
7–0
7–0
W
W
R
R
PPSJ7
PIEJ7
Pull Device Enable Port J
0 Pull-up or pull-down device is disabled.
1 Either a pull-up or pull-down device is enabled.
Polarity Select Port J
0 Falling edge on the associated port J pin sets the associated flag bit in the PIFJ register.
1 Rising edge on the associated port J pin sets the associated flag bit in the PIFJ register.
7
0
7
0
A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ
and if the port is used as general purpose input or as IIC port.
A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ
and if the port is used as input.
= Unimplemented or Reserved
= Unimplemented or Reserved
PPSJ6
PIEJ6
0
0
6
6
Figure 23-62. Port J Interrupt Enable Register (PIEJ)
Figure 23-61. Port J Polarity Select Register (PPSJ)
Table 23-54. PERJ Field Descriptions
Table 23-55. PPSJ Field Descriptions
PPSJ5
PIEJ5
5
0
5
0
PPSJ4
PIEJ4
0
0
4
4
Description
Description
3
0
0
3
0
0
PPSJ2
PIEJ2
0
0
2
2
PPSJ1
PIEJ1
1
0
1
0
PPSJ0
PIEJ0
0
0
0
0

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