MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 954

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with
Port J.
23.0.5.61 Port J Interrupt Flag Register (PIFJ)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSJ register. To clear this flag, write logic level “1” to the corresponding bit in the PIFJ
register. Writing a “0” has no effect.
23.0.5.62 Port AD0 Data Register 1 (PT1AD0)
Read: Anytime.
Write: Anytime.
956
PIEJ[7:4]
PIEJ[2:0]
PIFJ[7:4]
PIFJ[2:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
PT1AD07
PIFJ7
Interrupt Enable Port J
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Interrupt Flags Port J
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0
0
7
7
Writing a logic level “1” clears the associated flag.
= Unimplemented or Reserved
PT1AD06
PIFJ6
0
0
6
6
Figure 23-63. Port J Interrupt Flag Register (PIFJ)
Figure 23-64. Port AD0 Data Register 1 (PT1AD0)
PT1AD05
Table 23-56. PIEJ Field Descriptions
Table 23-57. PIEJ Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
PIFJ5
0
0
5
5
PT1AD04
PIFJ4
0
0
4
4
Description
Description
PT1AD03
0
0
0
3
3
PT1AD02
PIFJ2
0
0
2
2
PT1AD01
Freescale Semiconductor
PIFJ1
0
0
1
1
PT1AD00
PIFJ0
0
0
0
0

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