MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 955

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR1AD0[7:0]
Reset
Reset
This register is associated with AD0 pins PAD[23:10]. These pins can also be used as general
purpose I/O.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port
register, otherwise the value at the pins is read.
23.0.5.63 Port AD0 Data Direction Register 1 (DDR1AD0)
Read: Anytime.
Write: Anytime.
This register configures pins PAD[07:00] as either input or output.
23.0.5.64 Port AD0 Reduced Drive Register 1 (RDR1AD0)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each output pin PAD[07:00] as either full or reduced.
If the port is used as input this bit is ignored.
Field
7–0
W
W
R
R
DDR1AD07
RDR1AD07
7
0
7
0
Data Direction Port AD0 Register 1
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
Note: To use the digital input function on port AD0 the ATD0 digital input enable register (ATD0DIEN) has to
read on PTAD01 register, when changing the DDR1AD0 register.
be set to logic level “1”.
DDR1AD06
RDR1AD06
Figure 23-66. Port AD0 Reduced Drive Register 1 (RDR1AD0)
Figure 23-65. Port AD0 Data Direction Register 1 (DDR1AD0)
0
0
6
6
Table 23-58. DDR1AD0 Field Descriptions
DDR1AD05
RDR1AD05
5
0
5
0
DDR1AD04
RDR1AD04
0
0
4
4
Description
DDR1AD03
RDR1AD03
3
0
3
0
DDR1AD02
RDR1AD02
0
0
2
2
DDR1AD01
RDR1AD01
1
0
1
0
DDR1AD00
RDR1AD00
0
0
0
0