MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 992

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.4
Read: Anytime.
Write: Anytime.
24.0.5.5
Read: Anytime.
Write: Anytime.
994
DDRB[7:0]
Reset
Reset
Func.
Field
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
7–0
Alt.
W
W
associated pin values.
R
R
ECLKX2
DDRB7
XCLKS
Data Direction Port B — This register controls the data direction for port B. DDRB determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
PE7
Port B Data Direction Register (DDRB)
Port E Data Register (PORTE)
or
0
0
7
7
on PORTB after changing the DDRB register.
= Unimplemented or Reserved
DDRB6
MODB
PE6
0
0
6
6
Figure 24-6. Port B Data Direction Register (DDRB)
Figure 24-7. Port E Data Register (PORTE)
Table 24-7. DDRB Field Descriptions
DDRB5
MC9S12XDP512 Data Sheet, Rev. 2.21
MODA
PE5
0
0
5
5
DDRB4
ECLK
PE4
0
0
4
4
Description
EROMCTL
DDRB3
PE3
0
0
3
3
DDRB2
PE2
0
0
2
2
DDRB1
Freescale Semiconductor
PE1
IRQ
0
1
1
1
DDRB0
XIRQ
PE0
0
0
0
1

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