MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 998

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.12 Port K Data Direction Register (DDRK)
Read: Anytime.
Write: Anytime.
This register controls the data direction for port K. DDRK determines whether each pin (except PK6) is
an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0”
causes the associated pin to be a high-impedance input.
24.0.5.13 Port T Data Register (PTT)
Read: Anytime.
Write: Anytime.
1000
DDRK[7,5:0]
PK[7,5:0]
Reset
Reset
Field
Field
ECT
7–0
7–0
W
W
R
R
DDRK7
PTT7
IOC7
Port K — Port K pins 7–0 can be used as general-purpose I/O. If the data direction bits of the associated I/O pins
are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read
except for bit 6 which reads “0”.
Data Direction Port K
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
0
7
7
on PORTK after changing the DDRK register.
PTT6
IOC6
0
0
0
6
6
Figure 24-14. Port K Data Direction Register (DDRK)
Figure 24-15. Port T Data Register (PTT)
Table 24-15. PORTK Field Descriptions
Table 24-16. DDRK Field Descriptions
DDRK5
MC9S12XDP512 Data Sheet, Rev. 2.21
PTT5
IOC5
0
0
5
5
DDRK4
PTT4
IOC4
0
0
4
4
Description
Description
DDRK3
PTT3
IOC3
0
0
3
3
DDRK2
PTT2
IOC2
0
0
2
2
DDRK1
Freescale Semiconductor
PTT1
IOC1
0
0
1
1
DDRK0
PTT0
IOC0
0
0
0
0