MC56F8345VFGE Freescale Semiconductor, MC56F8345VFGE Datasheet

IC DSP 16BIT 60MHZ 128-LQFP

MC56F8345VFGE

Manufacturer Part Number
MC56F8345VFGE
Description
IC DSP 16BIT 60MHZ 128-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheet

Specifications of MC56F8345VFGE

Core Processor
56800
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
49
Program Memory Size
136KB (68K x 16)
Program Memory Type
FLASH
Ram Size
6K x 16
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
128-LQFP
Data Bus Width
16 bit
Processor Series
MC56F83xx
Core
56800E
Numeric And Arithmetic Format
Fixed-Point
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
49
Data Ram Size
8 KB
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Interface Type
SCI, SPI, CAN
Minimum Operating Temperature
- 40 C
For Use With
MC56F8367EVME - EVAL BOARD FOR MC56F83X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
56F8345/56F8145
Data Sheet
Preliminary Technical Data
MC56F8345
Rev. 17
01/2007
56F8300
16-bit Digital Signal Controllers
freescale.com

MC56F8345VFGE Summary of contents

Page 1

Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8345 Rev. 17 01/2007 freescale.com ...

Page 2

... IO Table 4-5. Removed min Table 4-10. Removed Table 10-6. with more recent data. Corrected typo in Table 10-12. Corrected Table 10-23 Table 10-1. Table 10-7 and clarified Section 12.3. Table 4-6. 10-1). Deleted formula for Max Ambient Freescale Semiconductor and Preliminary ...

Page 3

... Added the following note to the description of the TRST signal in Note: For normal operation, connect TRST directly to V debugging environment, TRST may be tied to V Please see http://www.freescale.com for the most current data sheet revision. Freescale Semiconductor Preliminary Description of Change Section 6.5.4. Added information/corrected state during reset in through a 2 ...

Page 4

... Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 5

... D or GPIOE SPI0 or 2 FlexCAN GPIOE 4 56F8345/56F8145 Block Diagram - 128 LQFP Freescale Semiconductor Preliminary • two Quadrature Decoders • FlexCAN module • Optional On-Chip Regulator • Two Serial Communication Interfaces (SCIs) • two Serial Peripheral Interface (SPIs) • four general-purpose Quad Timers • ...

Page 6

... Thermal Design Considerations . . . . . . . 167 12.2 Electrical Design Considerations . . . . . . 168 12.3 Power Distribution and I/O Ring Part 13 Ordering Information . . . . . . . . . . 170 56F8345 Technical Data, Rev. 17 Interrupt Timing . . . . . . . . . . . . . . . 142 Timing 144 Timing 149 Parameters . . . . . . . . . . . . . . . . . . . 152 Information . . . . . . . . . . . . . . . . . . . 158 Information . . . . . . . . . . . . . . . . . . . 161 Implementation . . . . . . . . . . . . . . . . 169 Freescale Semiconductor Preliminary ...

Page 7

... Differences Between Devices Table 1-1 outlines the key differences between the 56F8345 and 56F8145 devices. Feature Guaranteed Speed Program RAM Data Flash PWM CAN Quad Timer Quadrature Decoder Temperature Sensor Freescale Semiconductor Preliminary Table 1-1 Device Differences 56F8345 60MHz/60 MIPS 4KB 8KB 56F8345 Technical Data, Rev ...

Page 8

... Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) • two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines); SPI 1 can also be used as Quadrature Decoder 1 or Quad Timer B • Computer Operating Properly (COP)/Watchdog timer 8 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 9

... The 56F8345 controller includes 128KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM. A total of 8KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 ...

Page 10

... PWM functions to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned 10 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 11

... A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Award-Winning Development Environment ...

Page 12

... Peripheral User’s Manual for clarification on the operation of all three of these peripherals. 12 Figure 1-1 and Figure Part 2, Signal/Connection Descriptions, 56F8345 Technical Data, Rev. 17 1-2. Figure 1-1 illustrates how the Table 1-2 lists the Figure 1-2 to see which Freescale Semiconductor Preliminary ...

Page 13

... I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories. Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits. Freescale Semiconductor Preliminary pdb_m[15:0] pab[20:0] cdbw[31:0] ...

Page 14

... RESET SIM COP Reset COP 2 FlexCAN 13 PWMA SYNC Output 13 PWMB SYNC Output ch3i ch2i 2 Timer C ch3o ch2o 8 ADCB 8 ADCA 1 TEMP_SENSE Note: ADC A and ADC B use the same voltage reference circuit with and V REFP, REFMID REFN pins. Freescale Semiconductor , REFH REFLO Preliminary ...

Page 15

... Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m. 1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0. Freescale Semiconductor Preliminary Table 1-2 Bus Signal Names Function ...

Page 16

... Distribution Table 1-3 Chip Documentation Description Logic State True False True False are defined by individual product specifications. 56F8345 Technical Data, Rev. 17 Centers, or online Order Number DSP56800EERM MC56F8300UM MC56F83xxBLUM MC56F8345 MC56F8345E MC56F8145E Signal State 1 Voltage Asserted Deasserted Asserted Deasserted Freescale Semiconductor Preliminary at ...

Page 17

... Alternately, can function as Quad Timer pins or GPIO 3. Pins in this section can function as Quad Timer, SPI 1, orGPIO 4. EMI not functional in these packages; use as GPIO pins. Note: See Table 1-1 for 56F8145 functional differences. Freescale Semiconductor Preliminary Figure 2-1. In Table 2-2, each table row describes the signal or signals ...

Page 18

... Quadrature Decoder 0 or Quad Timer A or HOME0 (TA3, GPIOC7) GPIO SPI0 or GPIO Quadrature Decoder 1 or Quad Timer B or SPI1 or GPIO PWMA PWMB ADCA REF ADCB Temperature Sensor CAN Quad Timer C and D or GPIO Interrupt/ Program Control 1 (128-Pin LQFP) Freescale Semiconductor Preliminary ...

Page 19

... GPIOE TXD1 (GPIOD6) SCI1 or RXD1 (GPIOD7) GPIO JTAG/ EOnCE Port * EMI not functional in this package; use as GPIO pins Figure 2-2 56F8145 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. Freescale Semiconductor Preliminary V DD_IO DDA_ADC ...

Page 20

... Oscillator and PLL Power — This pin supplies 3.3V power to the OSC and to the internal regulator that in turn supplies the Phase Locked Loop. It must be connected to a clean analog power supply. Ground — These pins provide ground for chip logic and I/O drivers. 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 21

... PP CLKMODE 79 Input EXTAL 74 Input XTAL 73 Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset ADC Analog Ground — This pin supplies an analog ground to the ADC modules. Input On-Chip Regulator Disable — Tie this pin enable the on-chip regulator SS Tie this pin to V ...

Page 22

... A16 - A19 and EMI control signals are tri-stated when the external bus is inactive. After reset, the default state is GPIO. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOB_PUR register. Example: GPIOB1, clear bit 1 in the GPIOB_PUR register. 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 23

... Input/ Output D8 23 (GPIOF1 (GPIOF2) D10 26 (GPIOF3) Freescale Semiconductor Preliminary State During Signal Description Reset Input, Port B GPIO — This GPIO pin can be individually programmed pull- input or output pin. enabled Address Bus — A20 specifies one of the address lines for external program or data memory accesses ...

Page 24

... Port D GPIO — This GPIO pin can be individually programmed pull- input or output pin. enabled After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 6 in the GPIOD_PUR register. 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 25

... TMS 116 Schmitt Input TDI 117 Schmitt Input TDO 118 Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, Receive Data — SCI1 receive data input pull-up enabled Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. ...

Page 26

... TA1 — Timer A, Channel 1 Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PHASEB0. To deactivate the internal pull-up resistor, clear bit 5 of the GPIOC_PUR register. 56F8345 Technical Data, Rev the SS Freescale Semiconductor Preliminary ...

Page 27

... Input/ Output SCLK0 124 Schmitt Input/ Output (GPIOE4) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, Index — Quadrature Decoder 0, INDEX input pull-up enabled TA2 — Timer A, Channel 2 Port C GPIO — This GPIO pin can be individually programmed as an input or output pin ...

Page 28

... SPI module that the current transfer received. enabled Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SS0. To deactivate the internal pull-up resistor, clear bit 7 in the GPIOE_PUR register. 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 29

... Schmitt Input/ Output (MOSI1) Schmitt Input/ Output (GPIOC1) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, Phase A1 — Quadrature Decoder 1, PHASEA input for decoder pull-up 1. enabled TB0 — Timer B, Channel 0 SPI 1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners ...

Page 30

... In the 56F8345, the default state after reset is INDEX1. In the 56F8145, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 2 in the GPIOC_PUR register. 56F8345 Technical Data, Rev. 17 Part 6.5.8 for Freescale Semiconductor Preliminary ...

Page 31

... Input (GPIOC8) Schmitt Input/ ISA1 105 Output (GPIOC9) ISA2 106 (GPIOC10) Freescale Semiconductor Preliminary State During Signal Description Reset Input, Home — Quadrature Decoder 1, HOME input pull-up enabled TB3 — Timer B, Channel 3 SPI 1 Slave Select — In the master mode, this pin is used to arbitrate multiple masters ...

Page 32

... To deactivate the internal pull-up resistor, set the PWMB bit in the SIM_PUDR register. See Analog ANA0 - 3 — Analog inputs to ADC A, channel 0 Input 56F8345 Technical Data, Rev. 17 Part 6.5.6 for details. Part 6.5.6 for details. Part 6.5.6 for details. Part 6.5.6 for details. Freescale Semiconductor Preliminary ...

Page 33

... Input ANB5 101 ANB6 102 ANB7 103 TEMP_ 88 Output SENSE CAN_RX 121 Schmitt Input Freescale Semiconductor Preliminary State During Signal Description Reset Analog ANA4 - 7 — Analog inputs to ADC A, channel 1 Input Analog V — Analog Reference Voltage High. V REFH Input than or equal to V DDA_ADC. ...

Page 34

... They can be programmed to be level-sensitive or negative-edge triggered. To deactivate the internal pull-up resistor, set the IRQ bit in the SIM_PUDR register. See 56F8345 Technical Data, Rev. 17 Part 6.5.6 for details. Part 6.5.6 for details. Part 6.5.6 for details. Freescale Semiconductor Preliminary ...

Page 35

... Output EXTBOOT Internal Schmitt Ground Input EMI_MODE Internal Schmitt Ground Input Freescale Semiconductor Preliminary State During Signal Description Reset Input, Reset — This input is a direct hardware reset on the processor. pull-up When RESET is asserted low, the device is initialized and placed enabled in the reset state ...

Page 36

... Loss of Reference Loss of Reference Clock Detector Figure 3-1 OCCS Block Diagram Table 10-15. A recommended crystal oscillator circuit is shown 56F8345 Technical Data, Rev. 17 Figure 3-1 shows the ZSRC SYS_CLK2 Source to SIM Postscaler CLK ) 1,2,4,8 Bus Interface LCK Clock Interrupt Freescale Semiconductor Preliminary ...

Page 37

... A typical ceramic resonator circuit is shown in Refer to the supplier’s recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins. Freescale Semiconductor Preliminary EXTAL ...

Page 38

... EXTAL source with this configuration, the input “CLKMODE” should be high and COHL bit in V External the OSCTL register should be set Clock 56F8345 Technical Data, Rev. 17 CLKMODE = 0 Figure 3-4. The external clock Set OCCS_COHL bit high when using an Freescale Semiconductor Preliminary ...

Page 39

... OMR MA = Flash Secured EXTBOOT Pin 2,3 State Freescale Semiconductor Preliminary Table Table 4-1. 56F8145 128KB Erase / Program via Flash interface unit and word writes to CDBW — Erase / Program via Flash interface unit and word writes to CDBW. Data Flash can be read via either CDBR or XDB2, but not by both simultaneously — ...

Page 40

... EMI pins are not provided in the package; therefore, only the Mode 0 column is relevant. Note: Program RAM is NOT available on the 56F8145 device. 40 Chip Operating Mode Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is determined by the state of the EMI_MODE pin Chip Operating Mode 56F8345 Technical Data, Rev (Continued) Freescale Semiconductor Preliminary ...

Page 41

... VBA. In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or Freescale Semiconductor Preliminary 2, 3 EMI_MODE = 0 ...

Page 42

... Low Voltage Detector (power sense) P:$2A PLL P:$2C FM Access Error Interrupt P:$2E FM Command Complete P:$30 FM Command, data and address Buffers Empty Reserved P:$34 FLEXCAN Bus Off P:$36 FLEXCAN Error P:$38 FLEXCAN Wake Up 56F8345 Technical Data, Rev Interrupt Function 2 2 Freescale Semiconductor Preliminary ...

Page 43

... TMRD 54 0-2 TMRD 55 0-2 TMRC 56 0-2 TMRC 57 0-2 TMRC 58 0-2 TMRC 59 0-2 Freescale Semiconductor Preliminary Vector Base Address + P:$3A FLEXCAN Message Buffer Interrupt P:$3C GPIO F P:$3E GPIO E P:$40 GPIO D P:$42 GPIO C P:$44 GPIO B P:$46 GPIO A Reserved P:$4C SPI 1 Receiver Full ...

Page 44

... ADC A Conversion Complete / End of Scan P:$96 ADC B Zero Crossing or Limit Error P:$98 ADC A Zero Crossing or Limit Error P:$9A Reload PWM B P:$9C Reload PWM A P:$9E PWM B Fault P:$A0 PWM A Fault P:$A2 SW Interrupt LP 56F8345 Technical Data, Rev (Continued) Interrupt Function Freescale Semiconductor Preliminary ...

Page 45

... Flash Memory content, their state is maintained during power-down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual. These configuration parameters are located between $00_FFF7 and $00_FFFF. Freescale Semiconductor Preliminary Table 4-6 Data Memory Map 3 ...

Page 46

... Technical Data, Rev. 17 Data Memory FM_BASE + $14 Banked Registers Unbanked Registers FM_BASE + $00 8KB Note: Data Flash is NOT available in the 56F8145 device. Sector Size Page Size bits 512 x 16 bits 256 x 16 bits 256 x 16 bits bits 256 x 16 bits Register Name Freescale Semiconductor Preliminary ...

Page 47

... Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals. Note: Features in italics are NOT available in the 56F8145 device. Freescale Semiconductor Preliminary Register Name Reserved ...

Page 48

... X:$00 F400 FC X:$00 F800 56F8345 Technical Data, Rev. 17 Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 Freescale Semiconductor Preliminary ...

Page 49

... Chip Select Timing Control Register 6 CSTC 7 $17 Chip Select Timing Control Register 7 BCR $18 Bus Control Register Table 4-11 Quad Timer A Registers Address Map Register Acronym TMRA0_CMP1 Freescale Semiconductor Preliminary (EMI_BASE = $00 F020) Register Description (TMRA_BASE = $00 F040) Address Offset Register Description $0 Compare Register 1 56F8345 Technical Data, Rev. 17 ...

Page 50

... Comparator Load Register 2 $1A Comparator Status and Control Register Reserved $20 Compare Register 1 $21 Compare Register 2 $22 Capture Register $23 Load Register $24 Hold Register $25 Counter Register $26 Control Register $27 Status and Control Register $28 Comparator Load Register 1 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 51

... Quad Timer B is NOT available in the 56F8145 device Register Acronym TMRB0_CMP1 TMRB0_CMP2 TMRB0_CAP TMRB0_LOAD TMRB0_HOLD TMRB0_CNTR TMRB0_CTRL TMRB0_SCR TMRB0_CMPLD1 TMRB0_CMPLD2 TMRB0_COMSCR TMRB1_CMP1 Freescale Semiconductor Preliminary (TMRA_BASE = $00 F040) Address Offset Register Description $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved $30 Compare Register 1 $31 Compare Register 2 ...

Page 52

... Hold Register $25 Counter Register $26 Control Register $27 Status and Control Register $28 Comparator Load Register 1 $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved $30 Compare Register 1 $31 Compare Register 2 $32 Capture Register $33 Load Register 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 53

... TMRC0_HOLD TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 Freescale Semiconductor Preliminary (TMRB_BASE = $00 F080) Address Offset Register Description $34 Hold Register $35 Counter Register $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 ...

Page 54

... Counter Register $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 $3A Comparator Status and Control Register (TMRD_BASE = $00 F100) Address Offset $0 Compare Register 1 $1 Compare Register 2 56F8345 Technical Data, Rev. 17 Register Description Register Description Freescale Semiconductor Preliminary ...

Page 55

... TMRD1_HOLD TMRD1_CNTR TMRD1_CTRL TMRD1_SCR TMRD1_CMPLD1 TMRD1_CMPLD2 TMRD1_COMSCR TMRD2_CMP1 TMRD2_CMP2 TMRD2_CAP TMRD2_LOAD TMRD2_HOLD TMRD2_CNTR TMRD2_CTRL TMRD2_SCR TMRD2_CMPLD1 TMRD2_CMPLD2 Freescale Semiconductor Preliminary (TMRD_BASE = $00 F100) Address Offset $2 Capture Register $3 Load Register $4 Hold Register $5 Counter Register $6 Control Register $7 Status and Control Register $8 Comparator Load Register 1 ...

Page 56

... Output Control Register $4 Counter Register $5 Counter Modulo Register $6 Value Register 0 $7 Value Register 1 $8 Value Register 2 $9 Value Register 3 $A Value Register 4 $B Value Register 5 $C Dead Time Register $D Disable Mapping Register 1 56F8345 Technical Data, Rev. 17 Register Description Register Description Freescale Semiconductor Preliminary ...

Page 57

... PWMB_PMCNT PWMB_PWMCM PWMB_PWMVAL0 PWMB_PWMVAL1 PWMB_PWMVAL2 PWMB_PWMVAL3 PWMB_PWMVAL4 PWMB_PWMVAL5 PWMB_PMDEADTM PWMB_PMDISMAP1 PWMB_PMDISMAP2 PWMB_PMCFG PWMB_PMCCR PWMB_PMPORT PWMB_PMICCR Freescale Semiconductor Preliminary (PWMA_BASE = $00 F140) Address Offset Register Description $E Disable Mapping Register 2 $F Configure Register $10 Channel Control Register $11 Port Register $12 PWM Internal Correction Control Register (PWMB_BASE = $00 F160) ...

Page 58

... Position Difference Counter Register $4 Position Difference Counter Hold Register $5 Revolution Counter Register $6 Revolution Hold Register $7 Upper Position Counter Register $8 Lower Position Counter Register $9 Upper Position Hold Register $A Lower Position Hold Register $B Upper Initialization Register $C Lower Initialization Register 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 59

... IPR 9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP 0 IRQP 1 IRQP 2 IRQP 3 IRQP 4 IRQP 5 ICTL Freescale Semiconductor Preliminary (DEC1_BASE = $00 F190) Address Offset Register Description $D Input Monitor Register (ITCN_BASE = $00 F1A0) Address Offset Register Description $0 Interrupt Priority Register 0 $1 Interrupt Priority Register 1 $2 Interrupt Priority Register 2 ...

Page 60

... Low Limit Register 6 $18 Low Limit Register 7 $19 High Limit Register 0 $1A High Limit Register 1 $1B High Limit Register 2 $1C High Limit Register 3 $1D High Limit Register 4 $1E High Limit Register 5 $1F High Limit Register 6 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 61

... ADCB_ZCC ADCB_LST 1 ADCB_LST 2 ADCB_SDIS ADCB_STAT ADCB_LSTAT ADCB_ZCSTAT ADCB_RSLT 0 ADCB_RSLT 1 ADCB_RSLT 2 ADCB_RSLT 3 ADCB_RSLT 4 ADCB_RSLT 5 ADCB_RSLT 6 ADCB_RSLT 7 ADCB_LLMT 0 Freescale Semiconductor Preliminary (ADCA_BASE = $00 F200) Address Offset Register Description $20 High Limit Register 7 $21 Offset Register 0 $22 Offset Register 1 $23 Offset Register 2 $24 Offset Register 3 $25 ...

Page 62

... Offset Register 1 $23 Offset Register 2 $24 Offset Register 3 $25 Offset Register 4 $26 Offset Register 5 $27 Offset Register 6 $28 Offset Register 7 $29 Power Control Register $2A ADC Calibration Register (TSENSOR_BASE = $00 F270) Address Offset Register Description $0 Control Register 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 63

... Table 4-25 Serial Peripheral Interface 0 Registers Address Map Register Acronym SPI0_SPSCR SPI0_SPDSR SPI0_SPDRR SPI0_SPDTR Table 4-26 Serial Peripheral Interface 1 Registers Address Map Register Acronym SPI1_SPSCR SPI1_SPDSR SPI1_SPDRR Freescale Semiconductor Preliminary (SCI0_BASE = $00 F280) Address Offset Register Description $0 Baud Rate Register $1 Control Register Reserved $3 ...

Page 64

... Interrupt Assert Register $5 Interrupt Enable Register $6 Interrupt Polarity Register $7 Interrupt Pending Register $8 Interrupt Edge-Sensitive Register 56F8345 Technical Data, Rev. 17 Reset Value 0 x 3FFF 0 x 0000 0 x 0000 0 x 3FFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 Freescale Semiconductor Preliminary ...

Page 65

... GPIOB_RAWDATA Table 4-31 GPIOC Registers Address Map Register Acronym GPIOC_PUR GPIOC_DR GPIOC_DDR GPIOC_PER GPIOC_IAR GPIOC_IENR GPIOC_IPOLR GPIOC_IPR GPIOC_IESR GPIOC_PPMODE Freescale Semiconductor Preliminary (GPIOA_BASE = $00 F2E0) Address Offset Register Description $9 Push-Pull Mode Register $A Raw Data Input Register (GPIOB_BASE = $00 F300) Address Offset Register Description $0 ...

Page 66

... Reset Value 0 x 3FFF 0 x 0000 0 x 0000 0 x 3FFF 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 3FFF — Freescale Semiconductor Preliminary ...

Page 67

... Table 4-35 System Integration Module Registers Address Map Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL Freescale Semiconductor Preliminary (GPIOF_BASE = $00 F340) Address Offset Register Description $0 Pull-up Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register $5 ...

Page 68

... Hot temperature ADC reading of Temperature Sensor; value set during factory test $1B 16-Bit Information Option Register 1 Not used $1C 16-Bit Information Option Register 2 Room temperature ADC reading of Temperature Sensor; value set during factory test 56F8345 Technical Data, Rev. 17 Register Description Freescale Semiconductor Preliminary ...

Page 69

... FCRX14MASK_L FCRX15MASK_H FCRX15MASK_L FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $0 Module Configuration Register Reserved $3 Control Register 0 Register $4 Control Register 1 Register $5 Free-Running Timer Register $6 Maximum Message Buffer Configuration Register ...

Page 70

... Message Buffer 3 Data Register Reserved $60 Message Buffer 4 Control / Status Register $61 Message Buffer 4 ID High Register $62 Message Buffer 4 ID Low Register $63 Message Buffer 4 Data Register $64 Message Buffer 4 Data Register $65 Message Buffer 4 Data Register $66 Message Buffer 4 Data Register Reserved 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 71

... FCMB6_DATA FCMB6_DATA FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $68 Message Buffer 5 Control / Status Register $69 Message Buffer 5 ID High Register $6A Message Buffer 5 ID Low Register $6B Message Buffer 5 Data Register ...

Page 72

... Message Buffer 11 Data Register $9B Message Buffer 11 Data Register $9C Message Buffer 11 Data Register $9D Message Buffer 11 Data Register $9E Reserved $A0 Message Buffer 12 Control / Status Register $A1 Message Buffer 12 ID High Register $A2 Message Buffer 12 ID Low Register $A3 Message Buffer 12 Data Register 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 73

... FCMB15_DATA FCMB15_DATA 4.8 Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program. The Serial Bootloader application can be used to load a user application into the Program and Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description ...

Page 74

... Normal interrupt handling concatenates the VBA and the vector number to determine the vector address. In this way, an offset is generated into the vector table for each interrupt. 74 4-5, Interrupt Vector Table Contents. 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 75

... FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA. The core then fetches the instruction from the indicated vector adddress and not a JSR, the core starts its fast interrupt handling. Freescale Semiconductor Preliminary 1 Permitted Exceptions ...

Page 76

... The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB can wake it up. 76 any0 Level 0 82 -> Priority Encoder any3 Level 3 82 -> Priority Encoder 56F8345 Technical Data, Rev. 17 INT VAB CONTROL IPIC IACK SR[9:8] PIC_EN Freescale Semiconductor Preliminary ...

Page 77

... IRQP1 $12 IRQP2 $13 IRQP3 $14 IRQP4 $15 IRQP5 $16 ICTL $1D Freescale Semiconductor Preliminary Table 5-3 ITCN Register Summary (ITCN_BASE = $00F1A0) Register Name Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Priority Register 2 Interrupt Priority Register 3 Interrupt Priority Register 4 Interrupt Priority Register 5 Interrupt Priority Register 6 Interrupt Priority Register 7 ...

Page 78

... FAST INTERRUPT 0 VECTOR ADDRESS HIGH FAST INTERRUPT FAST INTERRUPT 1 VECTOR ADDRESS HIGH IRQB IRQA 1 IRQB STATE STATE INT_DIS EDG Freescale Semiconductor TRBUF IPL IRQA IPL 0 0 GPIOC IPL SPI0_XMIT IPL IPL TMRC1 IPL TMRA1 IPL 1 PEND- 1 ING [81] IRQA EDG Preliminary ...

Page 79

... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through disabled by default. • IRQ disabled (default) • IRQ is priority level 1 • IRQ is priority level 2 • IRQ is priority level 3 5.6.1.4 Reserved—Bits 9–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary STPCNT IPL 0 ...

Page 80

... EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through disabled by default. • IRQ disabled (default) • IRQ is priority level 56F8345 Technical Data, Rev RX_REG IPL TX_REG IPL TRBUF IPL Freescale Semiconductor Preliminary 0 0 ...

Page 81

... Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 Freescale Semiconductor Preliminary FMERR IPL ...

Page 82

... External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 82 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 83

... IRQ is priority level 1 • IRQ is priority level 2 5.6.4.4 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. Freescale Semiconductor Preliminary ...

Page 84

... They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.4.8 Reserved—Bits 1–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 84 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 85

... They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.5.4 Reserved—Bits 9–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary SPI1_RCV IPL ...

Page 86

... IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default SCI1_RCV SCI1_RERR IPL IPL IPL 56F8345 Technical Data, Rev SCI1_TIDL SCI1_XMIT SPI0_XMIT IPL IPL IPL Freescale Semiconductor Preliminary 0 0 ...

Page 87

... IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.6.5 Reserved—Bits 7–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Register Descriptions 87 ...

Page 88

... IRQ is priority level 1 • IRQ is priority level 2 5.6.7 Interrupt Priority Register 6 (IPR6) Base + $ Read TMRC0 TMRD3 IPL Write RESET Figure 5-9 Interrupt Priority Register 6 (IPR6 TMRD2 TMRD1 TMRD0 IPL IPL IPL 56F8345 Technical Data, Rev DEC0_XIRQ DEC0_HIRQ IPL IPL Freescale Semiconductor 0 IPL 0 Preliminary ...

Page 89

... IRQ is priority level 2 5.6.7.5 Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Register Descriptions 89 ...

Page 90

... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level TMRB2 IPL TMRB1 IPL TMRB0 IPL 56F8345 Technical Data, Rev TMRC3 IPL TMRC2 IPL TMRC1 IPL Freescale Semiconductor Preliminary 0 0 ...

Page 91

... Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Register Descriptions 91 ...

Page 92

... SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default SCI0_TIDL SCI0_XMIT IPL IPL 56F8345 Technical Data, Rev TMRA3 IPL TMRA2 IPL TMRA1 IPL IPL Freescale Semiconductor 0 0 Preliminary ...

Page 93

... IRQ is priority level 2 5.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Register Descriptions 93 ...

Page 94

... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level PWMA_RL PWMB_RL ADCA_ZC IPL ABCB_ZC IPL IPL IPL 56F8345 Technical Data, Rev ADCA_CC ADCB_CC IPL IPL Freescale Semiconductor Preliminary 0 0 ...

Page 95

... IRQ is priority level 2 5.6.10.7 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Register Descriptions 95 ...

Page 96

... Write RESET Figure 5-14 Fast Interrupt 0 Match Register (FIM0) 5.6.12.1 Reserved—Bits 15–7 This bit field is reserved or not implemented read as 0 and cannot be modified by writing VECTOR BASE ADDRESS Part 5.3.1 for details 56F8345 Technical Data, Rev FAST INTERRUPT Freescale Semiconductor Preliminary ...

Page 97

... Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0 The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. Freescale Semiconductor Preliminary 12 11 ...

Page 98

... Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1) 5.6.17.1 Reserved—Bits 15–5 This bit field is reserved or not implemented read as 0 and cannot be modified by writing FAST INTERRUPT 1 VECTOR ADDRESS LOW 56F8345 Technical Data, Rev FAST INTERRUPT FAST INTERRUPT 1 VECTOR ADDRESS HIGH Freescale Semiconductor Preliminary ...

Page 99

... IRQ Pending (PENDING)—Bits 32–17 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number Freescale Semiconductor Preliminary PENDING [16:2] ...

Page 100

... IRQ pending for this vector number • IRQ pending for this vector number 5.6.22 IRQ Pending 4 Register (IRQP4) Base + $ Read Write RESET Figure 5-24 IRQ Pending 4 Register (IRQP4) 100 PENDING [48:33 PENDING [64:49 PENDING [80:65 56F8345 Technical Data, Rev Freescale Semiconductor Preliminary ...

Page 101

... IRQ pending for this vector number • IRQ pending for this vector number 5.6.24 Reserved —Base + 17 5.6.25 Reserved —Base + 18 5.6.26 Reserved —Base + 19 5.6.27 Reserved —Base + 1A 5.6.28 Reserved —Base + 1B 5.6.29 Reserved —Base + 1C Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Register Descriptions ...

Page 102

... Normal operation (default) • All interrupts disabled 5.6.30.5 Reserved—Bit 4 This bit field is reserved or not implemented read as 1 and cannot be modified by writing. 102 VAB INT_DIS 56F8345 Technical Data, Rev IRQB STATE IRQA STATE IRQB EDG Freescale Semiconductor Preliminary 0 IRQA EDG 0 ...

Page 103

... IRQs with fixed priorities: • Illegal Instruction • SW Interrupt 3 • HW Stack Overflow • Misaligned Long Word Access • SW Interrupt 2 • SW Interrupt 1 • SW Interrupt 0 • SW Interrupt LP These interrupts are enabled at their fixed priority levels. Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Resets 103 ...

Page 104

... Software-initiated reset • Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control • System Control Register • Registers for software access to the JTAG ID of the chip 104 56F8345 Technical Data, Rev clock cycles. Freescale Semiconductor Preliminary ...

Page 105

... The reset state for MB and MA will depend on the Flash secured state. See information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. For additional information on the EX bit, see Manual. Note: The OMR is not a Memory Map register directly accessible in code through the acronym OMR. Freescale Semiconductor Preliminary ...

Page 106

... GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register 56F8345 Technical Data, Rev. 17 Section Location 6.5.1 6.5.2 6.5.3 6.5.3 6.5.3 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 6.5.9 6.5.10 6.5.10 Freescale Semiconductor Preliminary ...

Page 107

... Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.1.2 OnCE Enable (OnCE EBL)—Bit 5 • OnCE clock to 56800E core enabled when core TAP is enabled • OnCE clock to 56800E core is always enabled Freescale Semiconductor Preliminary ...

Page 108

... When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has occurred. This bit will be cleared by a Power-On Reset or by software. Writing this bit position will 108 56F8345 Technical Data, Rev SWR COPR EXTR POR 0 0 Freescale Semiconductor Preliminary ...

Page 109

... COP reset). 6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $11F4. Freescale Semiconductor Preliminary ...

Page 110

... Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR) 6.5.6.1 Reserved—Bit 15 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 110 Figure 6-8) corresponds to a functional group of pins. See RESET IRQ XBOOT PWMB PWMA0 56F8345 Technical Data, Rev CTRL JTAG Freescale Semiconductor Preliminary ...

Page 111

... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.13 JTAG—Bit 3 This bit controls the pull-up resistors on the TRST, TMS and TDI pins. Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Register Descriptions pin and this bit should be ...

Page 112

... Alternate GPIO_B Peripheral Function for A20 (A20)—Bit 6 • Peripheral output function of GPIOB[4] is defined to be A[20] • Peripheral output function of GPIOB[4] is defined to be the prescaler clock (FREF, see 112 A23 A22 A21 56F8345 Technical Data, Rev. 17 Figure 6- CLK A20 CLKOSEL DIS Figure Freescale Semiconductor Preliminary 0 0 3-4) ...

Page 113

... SPI inputs/outputs is made in the SIM_GPS and in conjunction with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function of GPIOC[3: programmed as decoder functions. This can be changed by altering the appropriate controls in the indicated registers. Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Register Descriptions ...

Page 114

... Peripheral User Manual for the definition of timer inputs based on the Quad Decoder mode configuration. — — 1 — See SPI controls for determining the direction of each of the SPI pins. — 1 — 56F8345 Technical Data, Rev. 17 I/O Pad Control 1 Comments Freescale Semiconductor Preliminary ...

Page 115

... This bit selects the alternate function for GPIOC0. • PHASEA1/TB0 (default) • SCLK1 6.5.9 Peripheral Clock Enable Register (SIM_PCE) The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip. Freescale Semiconductor Preliminary ...

Page 116

... Decoder 0 Enable (DEC0)—Bit 10 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) 116 TMRD TMRC TMRB TMRA 56F8345 Technical Data, Rev SCI1 SCI0 SPI1 SPI0 PWMB PWMA Freescale Semiconductor Preliminary 0 1 ...

Page 117

... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Register Descriptions 117 ...

Page 118

... The pipeline delay between setting this register set and using short I/O addressing with the new value is three cycles. 118 “ Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction 56F8345 Technical Data, Rev. 17 Instruction Portion Freescale Semiconductor Preliminary ...

Page 119

... Power modes permit system and/or peripheral clocks to be disabled when unused. Clock enables provide the means to disable individual clocks. Some peripherals provide further controls to disable unused subfunctions. Refer to Peripheral User Manual for further details. 6.7 Power-Down Modes Overview The 56F8345/56F8145 operate in one of three power-down modes, as shown in Freescale Semiconductor Preliminary ...

Page 120

... The only possible recoveries from Stop mode are: 1. CAN traffic (1st message will be lost) 2. Non-clocked interrupts 3. COP reset 4. External reset 5. Power-on reset D-FLOP D-FLOP C R Reset 56F8345 Technical Data, Rev. 17 Description 56800E STOP_DIS Note: Wait disable circuit is similar Freescale Semiconductor Preliminary ...

Page 121

... Peripheral User Manual for the state of the security bytes and the resulting state of security. When Flash security mode is enabled in accordance with the method described in the Flash Memory module specification, the device will disable the core EOnCE debug capabilities. Normal program execution is otherwise unaffected. Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Resets Part 6 ...

Page 122

... This mechanism completely reases all on-chip Flash, thus disabling Flash security. Access to this recovery mechanism is built into CodeWarrior via an instruction in memory configuration (.cfg) files. Add, or uncomment the following configuration command: unlock_flash_on_connect 1 For more information, please see CodeWarrior MC56F83xx/DSP5685x Family Targeting Manual. 122 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 123

... Register” section in the Flash Memory chapter of the 56F8300 Peripheral User Manual gives specific equations for calculating the correct values. SYS_CLK 2 FM_CLKDIV JTAG FM_ERASE Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. Freescale Semiconductor Preliminary Figure 7-1. FM_CLKDIV[6] will map to the Flash Memory input clock 7 FMCLKD 7 56F8345 Technical Data, Rev ...

Page 124

... TRST) and the device (by asserting external chip reset) to return to normal unsecured operation. 7.2.4 Product Analysis The recommended method of unsecuring a programmed device for product analysis of field failures is via 124 ( ) SYS_CLK (2) < < 200[kHz] (DIV + SYS_CLK (2) 200[kHz] < < (DIV + 1) 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 125

... Port GPIO Port Pins in Width 56F8345 Freescale Semiconductor Preliminary 4-29 through Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is Peripheral Function 6 pins - EMI Address pins - Can only be used as GPIO 8 pins - EMI Address pins - Not available in this package 5 pins - EMI Address pins - Can only be used as GPIO 3 pins - EMI Address pins - Not available in this package 56F8345 Technical Data, Rev ...

Page 126

... SCI1 N/A PWMB current sense SCI0 N/A SPI0 TMRC TMRD EMI Data N/A Reset Function EMI Address N/A GPIO N/A DEC1 / TMRB DEC0 / TMRA GPIO EMI Chip Selects SCI1 N/A PWMB current sense SCI0 N/A SPI0 TMRC GPIO Freescale Semiconductor Preliminary ...

Page 127

... Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIO Bit GPIOA Freescale Semiconductor Preliminary Peripheral Function 4 pins - EMI Data - Can only be used as GPIO 12 pins - EMI Data - Not available in this package Reset Function ...

Page 128

... A17 1 29 A18 30 1 A19 A20 / Prescaler_clock PHASEA1 / TB0 / SCLK1 2 10 PHASEB1 / TB1 / MOSI1 2 11 INDEX1 / TB2 / MISO1 2 12 HOME1 / TB3 / SS1 PHASEA0 / TA0 127 PHASEB0 / TA1 128 INDEX0 / TA2 1 HOME0 / TA3 2 ISA0 104 ISA1 105 ISA2 106 Freescale Semiconductor Preliminary ...

Page 129

... Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8345 / 56F8145 Pins in italics are NOT available in the 56F8145 device GPIO Port GPIO Bit GPIOD Freescale Semiconductor Preliminary Reset Function 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 Peripheral 7 Peripheral ...

Page 130

... Peripheral 7 Peripheral 8 Peripheral 9 Peripheral 10 Peripheral 11 Peripheral 12 Peripheral 13 Peripheral 56F8345 Technical Data, Rev. 17 Functional Signal Package Pin # TXD0 7 RXD0 8 SCLK0 124 MOSI0 126 MISO0 125 SS0 123 TC0 111 TC1 113 TD0 107 TD1 108 TD2 109 TD3 110 Freescale Semiconductor Preliminary ...

Page 131

... The 56F8345/56F8145 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture Freescale Semiconductor Preliminary Reset Function ...

Page 132

... OCR_DIS is High DD_CORE V Pin Groups Pin Groups 11, 12, 13 INA V Pin Groups OUT V Pin Group 56F8345 Technical Data, Rev. 17 Min Max Unit - 0.3 4 0.3 4 0.3 4 0.3 3.0 V -0.3 6.0 V -0.3 4.0 V -0.3 4 6.0 -0.3 6.0 V -40 125 °C -40 105 °C Freescale Semiconductor Preliminary ...

Page 133

... Pin Group 6: A8-15, GPIOB0-4, TD0-1 Pin Group 7: CLKO Pin Group 8: PWMA0-5, PWMB0-5 Pin Group 9: IRQA, IRQB, RESET, EXTBOOT, TRST,TMS, TDI, CAN_RX, EMI_MODE, FAULTA0-3, FAULTB0-3 Pin Group 10: TCK Pin Group 11: XTAL, EXTAL Pin Group 12: ANA0-7, ANB0-7 Pin Group 13: OCR_DIS, CLKMODE Freescale Semiconductor Preliminary ( SSA_ADC Symbol ...

Page 134

... JT 56F8345 Technical Data, Rev. 17 Typ Max Unit — — V — — V — — Value Unit 128-pin LQFP 50.8 °C/W 46.5 °C/W 43.9 °C/W 41.7 °C/W 13.9 °C/W 1.2 °C/W User-determined I/O θ ( Freescale Semiconductor Notes 2 2 1,2 1 Preliminary ...

Page 135

... Ambient Operating Temperature (Industrial) Flash Endurance (Automotive) (Program Erase Cycles) Flash Endurance (Industrial) (Program Erase Cycles) Flash Data Retention (Automotive) Note: Total chip source or sink current cannot exceed 200mA See Pin Groups listed in Table 10-1 Freescale Semiconductor Preliminary = SSA_ADC , DDA DDA_ADC ...

Page 136

... I OL OLmax μ +/- 2 3. μ 160 V = 3. μ +/- 2 DDA μ +/- 3 DDA μ - μ +/- 2 μ +/- 2 μ +/- 2 μ +/- 3 μ +/- 2 μ +/- 2 DDA μ 200 DDA μ +/- 2 3. OUT — V — — pF — — pF — — pF — — pF — Freescale Semiconductor Preliminary ...

Page 137

... On-Chip Regulator Enabled (OCR_DIS = Low) 1 Mode I DD_IO RUN1_MAC 155mA Wait3 91mA Stop1 5.8mA Stop2 5.1mA 1. No Output Switching 2. Includes Processor Core current supplied by internal voltage regulator Freescale Semiconductor Preliminary Symbol Min POR 1.75 V — EI2.5 V — EI3.3 I — bias , an interrupt is generated. ...

Page 138

... ADC powered off • PLL powered off • External Clock is off • All peripheral clocks are off • ADC powered off • PLL powered off Typical Max Unit — 2.75 V — 2.75 V — 2.75 V — 700 mA 5 μ — 30 minutes Freescale Semiconductor Preliminary ...

Page 139

... The ADC is not calibrated for the conversion of the Temperature Sensor trim value stored in the Flash Memory at FMOPT0 and FMOPT1. 3. See Application Note, AN1980, for methods to increase accuracy. 4. Assuming a 12-bit range from 0V to 3.3V. 5. Typical resolution calculated using equation, Freescale Semiconductor Preliminary Table 10-10. PLL Parameters Symbol Min T 0 ...

Page 140

... Figure 10-2 Signal States Symbol Min T 20 prog T 20 erase T 100 me 56F8345 Technical Data, Rev. 17 10-5. Unless otherwise specified, High 90% 50% 10% Rise Time and Data3 Valid Data3 Data Active Typ Max Unit μs — — — — ms — — ms Freescale Semiconductor Preliminary ...

Page 141

... An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f the 56F8300 Peripheral User Manual. Freescale Semiconductor Preliminary Symbol Min ...

Page 142

... IRW t 18T FAST 14T IG t 1.5T IW 56F8345 Technical Data, Rev. 17 Max Unit 120 ohms 250 ps 1.5 ns 300 ps 300 ps μA 290 μA 110 μA 1 1,2 Typical Unit See Figure Max — ns 10-4 — ns 10-5 — ns 10-6 — — ns 10-8 Freescale Semiconductor Preliminary ...

Page 143

... IG , IRQA IRQB Figure 10-6 External Level-Sensitive Interrupt Timing IRQA, IRQB A0–A15 Figure 10-7 Interrupt from Wait State Timing Freescale Semiconductor Preliminary Reset, Stop, Wait, Mode Select, and Interrupt Timing IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I/O ...

Page 144

... Freescale Semiconductor Preliminary ...

Page 145

... Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-9 SPI Master Timing (CPHA = 0) Freescale Semiconductor Preliminary 1 Table 10-17 SPI Timing (Continued) Symbol Min held High on master ...

Page 146

... SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 1) 146 SS is held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8345 Technical Data, Rev LSB in (ref Master LSB out t R Freescale Semiconductor Preliminary ...

Page 147

... SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-11 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output) MOSI (Input) Figure 10-12 SPI Slave Timing (CPHA = 1) Freescale Semiconductor Preliminary ELD Slave MSB out Bits 14– ...

Page 148

... P P OUTHL OUT Figure 10-13 Timer Timing Symbol Min 56F8345 Technical Data, Rev Max Unit See Figure — ns 10-13 — ns 10-13 — ns 10-13 — ns 10-13 P INHL P OUTHL 1, 2 Max Unit See Figure — ns 10-14 — ns 10-14 — ns 10-14 Freescale Semiconductor Preliminary ...

Page 149

... MAX 40MHz for the 56F8145 device. 3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. RXD SCI receive data pin (Input) Freescale Semiconductor Preliminary ...

Page 150

... T 5 — WAKEUP T WAKEUP Table 10-22 JTAG Timing Symbol Min Max f DC SYS_CLK SYS_CLK — — — DH 56F8345 Technical Data, Rev Unit See Figure 1 Mbps — μs 10-17 Unit See Figure MHz 10-18 MHz 10-18 ns 10-18 ns 10-19 ns 10-19 Freescale Semiconductor Preliminary ...

Page 151

... T = processor clock period (nominally 1/60MHz) TCK (Input – Figure 10-18 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-19 Test Access Port Timing Diagram Freescale Semiconductor Preliminary Table 10-22 JTAG Timing Symbol Min t — — TRST 1 ...

Page 152

... Technical Data, Rev. 17 Typ Max Unit — V REFH — 12 Bits +/- 2.4 +/- 3.2 LSB +/- 0.7 < +1 LSB GUARANTEED — 5 MHz — V REFH cycles AIC — — t cycles AIC 1 — t cycles AIC 5 — pF — — 1 — — mA μ +/- .004 +/- .015 Freescale Semiconductor — Preliminary ...

Page 153

... ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible. 6. Absolute error includes the effects of both gain error and offset error. 7. Please see the 56F8300 Peripheral User’s Manual for additional information on ADC calibration. 8. ENOB = (SINAD - 1.76)/6.02 Freescale Semiconductor Preliminary Symbol Min V — ...

Page 154

... Although not guaranteed believed that calibration will produce results similar to those shown above for any population of parts including those which represent processing and temperature extremes. 154 = 0.60V and 2.70V in 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 155

... One aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, V and the ADC clock frequency. REF Freescale Semiconductor Preliminary / 2, while the other charges to the analog input voltage. When the REFH 56F8345 Technical Data, Rev. 17 ...

Page 156

... This is also commonly described as C*V of the IO cell types used on the device reveal that the power-versus-load curve does have a non-zero Y-intercept. 156 REFH REFLO CMOS power dissipation corresponding to the 56F8345 Technical Data, Rev S 1pF 2 *F, although simulations on two Freescale Semiconductor Preliminary ...

Page 157

... For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. Freescale Semiconductor Preliminary Intercept 1.3 ...

Page 158

... LQFP. Please see freescale.com on the 56F8145 product page for the 128-pin LQFP Mechanical Case Outline (link located with orderable part number). 158 Figure 11-1. shows the package outline for the 128-pin LQFP, 56F8345 Technical Data, Rev. 17 Table 11-1 lists the pin-out for the Freescale Semiconductor Preliminary ...

Page 159

... DD_IO PWMB3 PWMB4 39 Figure 11-1 Top View, 56F8345 128-pin LQFP Package Table 11-1 56F8345 128-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. 1 INDEX0 2 HOME0 DD_IO Freescale Semiconductor Preliminary Orientation Mark Signal Name Pin No. 33 PWMB1 65 34 PWMB2 DD_IO 56F8345 Technical Data, Rev ...

Page 160

... TCK ANA4 116 TMS ANA5 117 TDI ANA6 118 TDO ANA7 119 V PP TEMP_SENSE 120 CAN_TX V 121 CAN_RX REFLO V 122 V REFN CAP V 123 SS0 REFMID V 124 SCLK0 REFP V 125 MISO0 REFH V 126 MOSI0 DDA_ADC V 127 PHASEA0 SSA_ADC Freescale Semiconductor 1 2 Preliminary ...

Page 161

... Low-profile Quad Flat Pack (LQFP). Figure 11-3 shows the mechanical parameters for this package, and 128-pin LQFP. Please see freescale.com on the 56F8145 product page for the 128-pin LQFP Mechanical Case Outline (link located with orderable part number). Freescale Semiconductor Preliminary Signal Name Pin No. 64 ...

Page 162

... Mark 56F8345 Technical Data, Rev. 17 ANB6 103 ANB5 ANB4 ANB3 ANB2 ANB1 ANB0 V SSA_ADC V DDA_ADC V REFH V REFP V REFMID V REFN V REFLO NC ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET RSTO V DD_IO V 3 CAP EXTAL XTAL V DDA_OSC_PLL OCR_DIS Freescale Semiconductor Preliminary ...

Page 163

... GPIOA3 19 1 GPIOA4 20 1 GPIOA5 GPIOF0 23 1 GPIOF1 24 1 GPIOF2 25 V DD_IO 1. Primary function is not available in this package configuration; GPIO function must be used instead Freescale Semiconductor Preliminary Signal Name Pin No. 33 PWMB1 65 34 PWMB2 DD_IO 37 PWMB3 69 38 PWMB4 70 39 PWMB5 ...

Page 164

... GPIOB3 31 GPIOB4 32 PWMB0 164 Signal Name Pin No DD_IO 56F8345 Technical Data, Rev. 17 Signal Name Pin No. Signal Name V 122 V REFN CAP V 123 SS0 REFMID V 124 SCLK0 REFP V 125 MISO0 REFH V 126 MOSI0 DDA_ADC V 127 PHASEA0 SSA_ADC ANB0 128 PHASEB0 Freescale Semiconductor 2 Preliminary ...

Page 165

... MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.35. Figure 11-3 128-pin LQFP Mechanical Information Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 56F8145 Package and Pin-Out Information MILLIMETERS DIM ...

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... Please see www.freescale.com for the most current case outline. 166 56F8345 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...

Page 167

... D where Thermocouple temperature on top of package ( T Ψ = Thermal characterization parameter ( Power dissipation in package (W) D Freescale Semiconductor Preliminary , can be obtained from the equation C/W) . For instance, the user can change the size of the heat θCA ) can be used to determine the junction temperature with a JT ...

Page 168

... Ceramic and tantalum capacitors tend to provide better DDA SSA. layers of the PCB with approximately 100μF, preferably with a high-grade 56F8345 Technical Data, Rev. 17 higher than pin on the device, and from the DD and V (GND and Freescale Semiconductor Preliminary ...

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... Flash, RAM and internal logic are powered from the core regulator output • and V 2 are not connected in the customer system PP PP • All circuitry, analog and digital, shares a common V V DDA_OSC_PLL REG OSC Freescale Semiconductor Preliminary , V REF DDA pins. bus CAP REG ...

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... Technical Data, Rev. 17 Ambient Temperature Order Number (MHz) Range 60 -40° 105° C MC56F8345VFG60 60 -40° 125° C MC56F8345MFG60 40 -40° 105° C MC56F8145VFG 60 -40° 105° C MC56F8345VFGE* 60 -40° 125° C MC56F8345MFGE* 40 -40° 105° C MC56F8145VFGE* Freescale Semiconductor Preliminary ...

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... THIS PAGE IS INTENTIONALLY BLANK Freescale Semiconductor Preliminary 56F8345 Technical Data, Rev. 17 Power Distribution and I/O Ring Implementation 171 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...

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