MC56F8345VFGE Freescale Semiconductor, MC56F8345VFGE Datasheet - Page 28

• Manufacturer Part Number: MC56F8345VFGE
• Description: IC DSP 16BIT 60MHZ 128-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8345VFGE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 49
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 128-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 49
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, CAN
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28
(GPIOE5)
(GPIOE6)
(GPIOE7)
MOSI0
MISO0
Signal
Name
SS0
Table 2-2 Signal and Package Information for the 128-Pin LQFP
Pin No.
126
125
123
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input/
Type
Input
56F8345 Technical Data, Rev. 17
disabled,
pull-up is
output is
In reset,
enabled
enabled
enabled
During
pull-up
pull-up
Reset
Input,
Input,
State
SPI 0 Master Out/Slave In — This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge the slave device uses to latch the data.
Port E GPIO — This GPIO pin can be individually programmed
as an input or output pin.
After reset, the default state is MOSI0.
To deactivate the internal pull-up resistor, clear bit 5 in the
GPIOE_PUR register.
SPI 0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line
of a slave device is placed in the high-impedance state if the
slave device is not selected. The slave device places data on the
MISO line a half-cycle before the clock edge the master device
uses to latch the data.
Port E GPIO — This GPIO pin can be individually programmed
as an input or output pin.
After reset, the default state is MISO0.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOE_PUR register.
SPI 0 Slave Select — SS0 is used in slave mode to indicate to
the SPI module that the current transfer is to be received.
Port E GPIO — This GPIO pin can be individually programmed
as an input or output pin.
After reset, the default state is SS0.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOE_PUR register.
Signal Description
Freescale Semiconductor
Preliminary