MC56F8345VFGE Freescale Semiconductor, MC56F8345VFGE Datasheet - Page 39

• Manufacturer Part Number: MC56F8345VFGE
• Description: IC DSP 16BIT 60MHZ 128-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8345VFGE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 49
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 128-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 49
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, CAN
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RAM and Flash memories are used in both spaces.
This section provides memory maps for:
On-chip memory sizes for each device are summarized in
identified in the “Use Restrictions” column of
Note: Data Flash and Program RAM are NOT available on the 56F8145 device.
4.2 Program Map
The Program memory map is located in
Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated
in
EXT_BOOT = EMI_MODE = 0 and cannot be changed in the 56F8345 or 56F8145.
Note: Program RAM is NOT available on the 56F8145 device.
Freescale Semiconductor
Preliminary
Program Flash
Data Flash
Program RAM
Data RAM
Program Boot Flash
Table
•
•
On-Chip Memory
Flash Secured
OMR MB =
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
State
4-2.
0
0
1
2,3
EXTBOOT Pin
OMR MA =
56F8345
0
1
0
128KB
8KB
4KB
8KB
8KB
Table 4-1 Chip Memory Configurations
Table 4-2 OMR MB/MA Value at Reset
Mode 0 – Internal Boot; EMI is configured to use 16 address lines; Flash
Memory is secured; external P-space is not allowed; the EOnCE is disabled
Not valid; cannot boot externally if the Flash is secured and will actually
configure to 00 state
Mode 0 – Internal Boot; EMI is configured to use 16 address lines
56F8345 Technical Data, Rev. 17
Table
56F8145
128KB
8KB
8KB
—
—
Table
4-4. The operating mode control bits (MA and MB) in the
CDBW
Erase / Program via Flash interface unit and word writes to
CDBW. Data Flash can be read via either CDBR or XDB2,
but not by both simultaneously
None
Erase / Program via Flash Interface unit and word writes to
CDBW
4-1.
Erase / Program via Flash interface unit and word writes to
None
Chip Operating Mode
Table
4-1. Flash memories’ restrictions are
Use Restrictions
1
Program Map
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