MC56F8345VFGE Freescale Semiconductor, MC56F8345VFGE Datasheet - Page 69

• Manufacturer Part Number: MC56F8345VFGE
• Description: IC DSP 16BIT 60MHZ 128-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8345VFGE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 49
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 128-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 49
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SCI, SPI, CAN
• Minimum Operating Temperature: - 40 C
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Preliminary
FCMCR
FCCTL0
FCCTL1
FCTMR
FCMAXMB
FCRXGMASK_H
FCRXGMASK_L
FCRX14MASK_H
FCRX14MASK_L
FCRX15MASK_H
FCRX15MASK_L
FCSTATUS
FCIMASK1
FCIFLAG1
FCR/T_ERROR_CNTRS
FCMB0_CONTROL
FCMB0_ID_HIGH
FCMB0_ID_LOW
FCMB0_DATA
FCMB0_DATA
FCMB0_DATA
FCMB0_DATA
FCMSB1_CONTROL
Register Acronym
FlexCAN is NOT available in the 56F8145 device
Table 4-38 FlexCAN Registers Address Map
Address Offset
56F8345 Technical Data, Rev. 17
(FC_BASE = $00 F800)
$11
$12
$13
$40
$41
$42
$43
$44
$45
$46
$48
$10
$C
$D
$A
$B
$0
$3
$4
$5
$6
$8
$9
Module Configuration Register
Reserved
Control Register 0 Register
Control Register 1 Register
Free-Running Timer Register
Maximum Message Buffer Configuration Register
Reserved
Receive Global Mask High Register
Receive Global Mask Low Register
Receive Buffer 14 Mask High Register
Receive Buffer 14 Mask Low Register
Receive Buffer 15 Mask High Register
Receive Buffer 15 Mask Low Register
Reserved
Error and Status Register
Interrupt Masks 1 Register
Interrupt Flags 1 Register
Receive and Transmit Error Counters Register
Reserved
Reserved
Reserved
Message Buffer 0 Control / Status Register
Message Buffer 0 ID High Register
Message Buffer 0 ID Low Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Reserved
Message Buffer 1 Control / Status Register
Register Description
Peripheral Memory Mapped Registers
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