MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 118

IC MCU 16BIT 1M FLASH 112-LQFP

MC9S12XEP100CAL

Manufacturer Part Number
MC9S12XEP100CAL
Description
IC MCU 16BIT 1M FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEP100CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
64 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
91
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 12-bit
Package
112LQFP
Family Name
HCS12X
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|2.8|5 V
For Use With
EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
1. Read:Anytime in single-chip modes.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.12
2.3.13
118
Address 0x0009 (PRR)
Address 0x000C (PRR)
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Write:Anytime, except BKPUE which is writable in Special Test Mode only.
DDRE
Field
Reset
Reset
7-2
1-0
W
W
R
R
Port E Data Direction—
This register controls the data direction of pins 7 through 2.
The external bus function controls the data direction for the associated pins. In this case the data direction bits will
not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
Reserved—
Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits 1
and 0, can be read regardless of whether the alternate interrupt function is enabled.
DDRE7
PUPKE
Port E Data Direction Register (DDRE)
S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR)
0
1
7
7
Figure 2-11. S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR)
= Unimplemented or Reserved
= Unimplemented or Reserved
DDRE6
BKPUE
0
1
6
6
Figure 2-10. Port E Data Direction Register (DDRE)
Table 2-13. DDRE Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
DDRE5
0
0
0
5
5
DDRE4
PUPEE
0
1
4
4
Description
DDRE3
PUPDE
3
0
3
0
DDRE2
PUPCE
0
0
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
PUPBE
0
0
0
1
1
PUPAE
0
0
0
0
0
(1)
(1)

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