MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 1237

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

During power sequencing V
V
V
A.6
This section summarizes the electrical characteristics of the various startup scenarios for oscillator and
phase-locked loop (PLL).
A.6.1
Table A-23
startup behavior can be found in the Clock and Reset Generator (CRG) block description
1
2
A.6.1.1
The release level V
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
Freescale Semiconductor
Conditions are shown in
Num C
DDR
RH
This is the time between RESET deassertion and start of CPU code execution.
Including voltage regulator startup; V
1
2
3
4
V
V
V
power up must follow V
DDA
DDR,
DDX
and V
D Reset input pulse width, minimum input time
D Startup from reset
D Wait recovery startup time
D Fast wakeup from STOP
V
Reset, Oscillator and PLL
summarizes several startup characteristics explained in this section. Detailed description of the
Startup
DDX
POR
must be powered up together adhering to the operating conditions differential.
PORR
Table
and the assert level V
CQOUT
A-4unless otherwise noted
Figure A-4. MC9S12XE-Family Power Sequencing
DDA
DDA
2
Rating
MC9S12XE-Family Reference Manual Rev. 1.23
DD
can be powered up before V
no valid oscillation is detected, the MCU will start using the internal self
to avoid current injection.
Table A-23. Startup Characteristics
/V
DDF
>= 0
filter capacitors 220 nF, V
PORA
are derived from the V
uposc
.
Symbol
PW
t
t
WRS
t
RST
DDR
fws
DD35
RSTL
, V
= 5 V, T= 25°C
DDX
Min
192
—
—
2
.
DD
Appendix A Electrical Characteristics
supply. They are also valid
Typ
50
—
—
—
4000
Max
100
14
—
1
t
Unit
n
t
t
µs
osc
cyc
bus
1237